Re: [PATCH v2] drm/msm/dpu: Fall back to a single DSC encoder (1:1:1) on small SoCs

2025-01-23 Thread Jessica Zhang
On 1/22/2025 8:23 AM, Marijn Suijten wrote: Some SoCs such as SC7280 (used in the Fairphone 5) have only a single DSC "hard slice" encoder. The current hardcoded use of 2:2:1 topology (2 LM and 2 DSC for a single interface) make it impossible to use Display Stream Compression panels with main

Re: [PATCH v2] drm/msm/dpu: Fall back to a single DSC encoder (1:1:1) on small SoCs

2025-01-23 Thread Luca Weiss
On Wed Jan 22, 2025 at 5:23 PM CET, Marijn Suijten wrote: > Some SoCs such as SC7280 (used in the Fairphone 5) have only a single > DSC "hard slice" encoder. The current hardcoded use of 2:2:1 topology > (2 LM and 2 DSC for a single interface) make it impossible to use > Display Stream Compression

Re: [PATCH v2] drm/msm/dpu: Fall back to a single DSC encoder (1:1:1) on small SoCs

2025-01-22 Thread Dmitry Baryshkov
On Wed, Jan 22, 2025 at 05:23:44PM +0100, Marijn Suijten wrote: > Some SoCs such as SC7280 (used in the Fairphone 5) have only a single > DSC "hard slice" encoder. The current hardcoded use of 2:2:1 topology > (2 LM and 2 DSC for a single interface) make it impossible to use > Display Stream Compr

[PATCH v2] drm/msm/dpu: Fall back to a single DSC encoder (1:1:1) on small SoCs

2025-01-22 Thread Marijn Suijten
Some SoCs such as SC7280 (used in the Fairphone 5) have only a single DSC "hard slice" encoder. The current hardcoded use of 2:2:1 topology (2 LM and 2 DSC for a single interface) make it impossible to use Display Stream Compression panels with mainline, which is exactly what's installed on the Fa