RE: [PATCH v2] drm/bridge:anx7625: Enable DSC feature

2025-04-05 Thread Xin Ji
> > > > 4K30(3840x2160 30Hz) timing pixel clock around 297M, for 24bits > > > > RGB pixel data format, total transport bandwidth need 297M*24(at > > > > least > > > > 7.2Gbps) more than anx7625 mipi rx lane bandwidth(maximum 6Gbps, > > > > 4lanes, each lane 1.5Gbps). Without DSC function, anx7625 c

RE: [PATCH v2] drm/bridge:anx7625: Enable DSC feature

2025-04-05 Thread Xin Ji
> > > > > 4K30(3840x2160 30Hz) timing pixel clock around 297M, for 24bits > > > > > RGB pixel data format, total transport bandwidth need 297M*24(at > > > > > least > > > > > 7.2Gbps) more than anx7625 mipi rx lane bandwidth(maximum 6Gbps, > > > > > 4lanes, each lane 1.5Gbps). Without DSC function,

Re: [PATCH v2] drm/bridge:anx7625: Enable DSC feature

2025-03-31 Thread Dmitry Baryshkov
On Mon, Mar 31, 2025 at 10:28:00AM +0300, Dmitry Baryshkov wrote: > On Mon, Mar 31, 2025 at 05:44:58AM +, Xin Ji wrote: > > > > 4K30(3840x2160 30Hz) timing pixel clock around 297M, for 24bits RGB > > > > pixel data format, total transport bandwidth need 297M*24(at least > > > > 7.2Gbps) more th

Re: [PATCH v2] drm/bridge:anx7625: Enable DSC feature

2025-03-31 Thread Dmitry Baryshkov
On Mon, Mar 31, 2025 at 05:44:58AM +, Xin Ji wrote: > > > 4K30(3840x2160 30Hz) timing pixel clock around 297M, for 24bits RGB > > > pixel data format, total transport bandwidth need 297M*24(at least > > > 7.2Gbps) more than anx7625 mipi rx lane bandwidth(maximum 6Gbps, > > > 4lanes, each lane 1

RE: [PATCH v2] drm/bridge:anx7625: Enable DSC feature

2025-03-30 Thread Xin Ji
> > 4K30(3840x2160 30Hz) timing pixel clock around 297M, for 24bits RGB > > pixel data format, total transport bandwidth need 297M*24(at least > > 7.2Gbps) more than anx7625 mipi rx lane bandwidth(maximum 6Gbps, > > 4lanes, each lane 1.5Gbps). Without DSC function, anx7625 cannot > > receive 4K30 v

Re: [PATCH v2] drm/bridge:anx7625: Enable DSC feature

2025-03-30 Thread Dmitry Baryshkov
On Thu, Mar 27, 2025 at 07:56:15PM +0800, Xin Ji wrote: > 4K30(3840x2160 30Hz) timing pixel clock around 297M, for 24bits RGB > pixel data format, total transport bandwidth need 297M*24(at least > 7.2Gbps) more than anx7625 mipi rx lane bandwidth(maximum 6Gbps, > 4lanes, each lane 1.5Gbps). Without

[PATCH v2] drm/bridge:anx7625: Enable DSC feature

2025-03-27 Thread Xin Ji
4K30(3840x2160 30Hz) timing pixel clock around 297M, for 24bits RGB pixel data format, total transport bandwidth need 297M*24(at least 7.2Gbps) more than anx7625 mipi rx lane bandwidth(maximum 6Gbps, 4lanes, each lane 1.5Gbps). Without DSC function, anx7625 cannot receive 4K30 video timing. When d