Il 22/11/24 07:23, CK Hu (胡俊光) ha scritto:
Hi, Angelo:
On Fri, 2024-11-22 at 11:54 +0800, CK Hu wrote:
Hi, Angelo:
On Wed, 2024-11-20 at 13:44 +0100, AngeloGioacchino Del Regno wrote:
External email : Please do not click links or open attachments until you have
verified the sender or the con
Setting the TVD PLL clock requires to multiply the target pixel
clock by a specific constant factor to achieve the target PLL
frequency, and this is done to reduce jitter to acceptable levels.
On all MediaTek SoCs, the factor is not retrieved by any real kind
of calculation but rather by checking
