On Thu, Jan 18, 2024 at 3:01 AM Qiang Yu wrote:
>
> Do we need same for GP?
I don't have an issue reproducer for gp so far, but the hardware does
have the same bit and the mali driver does it for both gp and pp, so I
think we can also add it to gp.
Do we need same for GP?
Regards,
Qiang
On Wed, Jan 17, 2024 at 11:12 AM Erico Nunes wrote:
>
> This is required for reliable hard resets. Otherwise, doing a hard reset
> while a task is still running (such as a task which is being stopped by
> the drm_sched timeout handler) may result in random
On Tue, Jan 16, 2024 at 7:12 PM Erico Nunes wrote:
>
> This is required for reliable hard resets. Otherwise, doing a hard reset
> while a task is still running (such as a task which is being stopped by
> the drm_sched timeout handler) may result in random mmu write timeouts
> or lockups which caus
This is required for reliable hard resets. Otherwise, doing a hard reset
while a task is still running (such as a task which is being stopped by
the drm_sched timeout handler) may result in random mmu write timeouts
or lockups which cause the entire gpu to hang.
Signed-off-by: Erico Nunes
---
dr
