On Mon, Mar 01, 2021 at 02:15:12PM +0530, kgu...@codeaurora.org wrote:
> On 2021-02-26 22:56, Daniel Thompson wrote:
> > On Fri, Feb 26, 2021 at 05:42:24PM +0530, Kiran Gunda wrote:
> > > As per the current implementation, after FSC (Full Scale Current)
> > > and brightness update the sync bits are
On 2021-02-26 22:56, Daniel Thompson wrote:
On Fri, Feb 26, 2021 at 05:42:24PM +0530, Kiran Gunda wrote:
As per the current implementation, after FSC (Full Scale Current)
and brightness update the sync bits are transitioned from 1 to 0.
This still seems to incorrectly describe the current beha
On Fri, Feb 26, 2021 at 05:42:24PM +0530, Kiran Gunda wrote:
> As per the current implementation, after FSC (Full Scale Current)
> and brightness update the sync bits are transitioned from 1 to 0.
This still seems to incorrectly describe the current behaviour.
Surely in most cases (i.e. every tim
As per the current implementation, after FSC (Full Scale Current)
and brightness update the sync bits are transitioned from 1 to 0.
But, the FSC and brightness sync takes place during a 0 to 1
transition of the sync bits. So the hardware team recommends a
clear-then-set approach in order to guarant
