On 7/12/2025 1:33 AM, Krzysztof Kozlowski wrote:
> On 11/07/2025 20:33, Williams, Gregory wrote:
>> +
>> +maintainers:
>> + - Gregory Williams
>> +
>> +description:
>> + The AMD AI Engine is a tile processor with many cores (up to 400) that
>> + can run in parallel.
On 11/07/2025 20:33, Williams, Gregory wrote:
> +
> +maintainers:
> + - Gregory Williams
> +
> +description:
> + The AMD AI Engine is a tile processor with many cores (up to 400) that
> + can run in parallel. The data routing between cores is configured
> throug
On 7/10/2025 3:38 PM, Krzysztof Kozlowski wrote:
> On 10/07/2025 21:03, Williams, Gregory wrote:
>> On 7/3/2025 12:48 AM, Krzysztof Kozlowski wrote:
>>> On 02/07/2025 17:56, Gregory Williams wrote:
In the device tree, there will be device node for the AI engine device,
and device nodes fo
On 10/07/2025 21:03, Williams, Gregory wrote:
> On 7/3/2025 12:48 AM, Krzysztof Kozlowski wrote:
>> On 02/07/2025 17:56, Gregory Williams wrote:
>>> In the device tree, there will be device node for the AI engine device,
>>> and device nodes for the statically configured AI engine apertures.
>>
>>
On 7/3/2025 12:48 AM, Krzysztof Kozlowski wrote:
> On 02/07/2025 17:56, Gregory Williams wrote:
>> In the device tree, there will be device node for the AI engine device,
>> and device nodes for the statically configured AI engine apertures.
>
> No, describe the hardware, not DTS.
>
>> Apertures
On 02/07/2025 17:56, Gregory Williams wrote:
> In the device tree, there will be device node for the AI engine device,
> and device nodes for the statically configured AI engine apertures.
No, describe the hardware, not DTS.
> Apertures are an isolated set of columns with in the AI engine device
In the device tree, there will be device node for the AI engine device,
and device nodes for the statically configured AI engine apertures.
Apertures are an isolated set of columns with in the AI engine device
with their own address space and interrupt.
Signed-off-by: Gregory Williams
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.../bi
