On Thu, Feb 12, 2015 at 02:01:23PM +0800, Liu Ying wrote:
> Liu Ying (20):
> clk: divider: Correct parent clk round rate if no bestdiv is normally
> found
> ARM: imx6q: Add GPR3 MIPI muxing control register field shift bits
> definition
> ARM: imx6q: clk: Add the video_27m clock
>
Hi,
This version mainly addresses the comments from Philipp Zabel on v8.
The comments include
a. A common compatible string "snps,dw-mipi-dsi" should be appended to all SoCs'
MIPI DSI device tree documentations and nodes.
b. Clean up the common clocks needed by the Synopsys DesignWare MIPI DSI
