On Wed, May 04, 2016 at 11:34:39PM +0530, Archit Taneja wrote:
>
>
> On 5/4/2016 7:14 PM, Rob Herring wrote:
> >On Tue, May 03, 2016 at 04:28:01PM +0530, Archit Taneja wrote:
> >>The PLL in the DSI PHY block generates 2 clock outputs (Byte and Pixel
> >>clocks) that are fed into the Multimedia Cl
On 5/4/2016 7:14 PM, Rob Herring wrote:
> On Tue, May 03, 2016 at 04:28:01PM +0530, Archit Taneja wrote:
>> The PLL in the DSI PHY block generates 2 clock outputs (Byte and Pixel
>> clocks) that are fed into the Multimedia Clock Controller (MMCC). The MMCC
>> uses these as source clocks for some
On Tue, May 03, 2016 at 04:28:01PM +0530, Archit Taneja wrote:
> The PLL in the DSI PHY block generates 2 clock outputs (Byte and Pixel
> clocks) that are fed into the Multimedia Clock Controller (MMCC). The MMCC
> uses these as source clocks for some of its RCGs to generate clocks that
> finally f
The PLL in the DSI PHY block generates 2 clock outputs (Byte and Pixel
clocks) that are fed into the Multimedia Clock Controller (MMCC). The MMCC
uses these as source clocks for some of its RCGs to generate clocks that
finally feed to the DSI host controller.
Use the assigned clocks DT bindings to
