Re: [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level

2023-04-24 Thread Tvrtko Ursulin
On 23/04/2023 07:52, Yang, Fei wrote: On 20/04/2023 00:00, fei.y...@intel.com wrote: From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index which really controls the caching behavior in PTE has far more le

Re: [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level

2023-04-24 Thread Tvrtko Ursulin
On 23/04/2023 07:12, Yang, Fei wrote: On 20/04/2023 00:00, fei.y...@intel.com wrote: From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index which really controls the caching behavior in PTE has far more le

RE: [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level

2023-04-22 Thread Yang, Fei
> On 20/04/2023 00:00, fei.y...@intel.com wrote: >> From: Fei Yang >> >> Currently the KMD is using enum i915_cache_level to set caching policy for >> buffer objects. This is flaky because the PAT index which really controls >> the caching behavior in PTE has far more levels than what's defined in

RE: [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level

2023-04-22 Thread Yang, Fei
> On 20/04/2023 00:00, fei.y...@intel.com wrote: >> From: Fei Yang >> >> Currently the KMD is using enum i915_cache_level to set caching policy >> for buffer objects. This is flaky because the PAT index which really >> controls the caching behavior in PTE has far more levels than what's >> defined

Re: [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level

2023-04-21 Thread Tvrtko Ursulin
On 20/04/2023 00:00, fei.y...@intel.com wrote: From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index which really controls the caching behavior in PTE has far more levels than what's defined in the enum. I

Re: [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level

2023-04-21 Thread Tvrtko Ursulin
On 20/04/2023 00:00, fei.y...@intel.com wrote: From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index which really controls the caching behavior in PTE has far more levels than what's defined in the enum.

Re: [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level

2023-04-21 Thread Tvrtko Ursulin
On 20/04/2023 00:00, fei.y...@intel.com wrote: From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index which really controls the caching behavior in PTE has far more levels than what's defined in the enum. I

Re: [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level

2023-04-20 Thread Tvrtko Ursulin
On 20/04/2023 11:13, Andrzej Hajda wrote: On 20.04.2023 01:00, fei.y...@intel.com wrote: From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index which really controls the caching behavior in PTE has far m

Re: [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level

2023-04-20 Thread Andrzej Hajda
On 20.04.2023 01:00, fei.y...@intel.com wrote: From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index which really controls the caching behavior in PTE has far more levels than what's defined in the enum. In

[PATCH 7/8] drm/i915: use pat_index instead of cache_level

2023-04-19 Thread fei . yang
From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index which really controls the caching behavior in PTE has far more levels than what's defined in the enum. In addition, the PAT index is platform dependent, ha

Re: [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level

2023-04-19 Thread Andi Shyti
Hi Fei, > Currently the KMD is using enum i915_cache_level to set caching policy for > buffer objects. This is flaky because the PAT index which really controls > the caching behavior in PTE has far more levels than what's defined in the > enum. In addition, the PAT index is platform dependent, ha

[PATCH 7/8] drm/i915: use pat_index instead of cache_level

2023-04-19 Thread fei . yang
From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index which really controls the caching behavior in PTE has far more levels than what's defined in the enum. In addition, the PAT index is platform dependent, ha

[PATCH 7/8] drm/i915: use pat_index instead of cache_level

2023-04-19 Thread fei . yang
From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index which really controls the caching behavior in PTE has far more levels than what's defined in the enum. In addition, the PAT index is platform dependent, ha

Re: [Intel-gfx] [PATCH 7/8] drm/i915: use pat_index instead of cache_level

2023-04-19 Thread Andi Shyti
Hi Fei, On Sun, Apr 16, 2023 at 11:25:02PM -0700, fei.y...@intel.com wrote: > From: Fei Yang > > Currently the KMD is using enum i915_cache_level to set caching policy for > buffer objects. This is flaky because the PAT index which really controls > the caching behavior in PTE has far more level

[PATCH 7/8] drm/i915: use pat_index instead of cache_level

2023-04-16 Thread fei . yang
From: Fei Yang Currently the KMD is using enum i915_cache_level to set caching policy for buffer objects. This is flaky because the PAT index which really controls the caching behavior in PTE has far more levels than what's defined in the enum. In addition, the PAT index is platform dependent, ha