[PATCH 5/7 v6] drm/i915/intel_i2c: use INDEX cycles for i2c read transactions

2012-03-29 Thread Daniel Kurtz
On Thu, Mar 29, 2012 at 2:52 AM, Chris Wilson wrote: > On Thu, 29 Mar 2012 02:26:37 +0800, Daniel Kurtz > wrote: >> It is very common for an i2c device to require a small 1 or 2 byte write >> followed by a read. ?For example, when reading from an i2c EEPROM it is >> common to write and address,

[PATCH 5/7 v6] drm/i915/intel_i2c: use INDEX cycles for i2c read transactions

2012-03-29 Thread Daniel Vetter
On Thu, Mar 29, 2012 at 04:37:18PM +0800, Daniel Kurtz wrote: > On Thu, Mar 29, 2012 at 2:52 AM, Chris Wilson > wrote: > > On Thu, 29 Mar 2012 02:26:37 +0800, Daniel Kurtz > > wrote: > >> It is very common for an i2c device to require a small 1 or 2 byte write > >> followed by a read. ?For exam

Re: [PATCH 5/7 v6] drm/i915/intel_i2c: use INDEX cycles for i2c read transactions

2012-03-29 Thread Daniel Kurtz
On Thu, Mar 29, 2012 at 2:52 AM, Chris Wilson wrote: > On Thu, 29 Mar 2012 02:26:37 +0800, Daniel Kurtz wrote: >> It is very common for an i2c device to require a small 1 or 2 byte write >> followed by a read.  For example, when reading from an i2c EEPROM it is >> common to write and address, off

[PATCH 5/7 v6] drm/i915/intel_i2c: use INDEX cycles for i2c read transactions

2012-03-29 Thread Daniel Kurtz
It is very common for an i2c device to require a small 1 or 2 byte write followed by a read. For example, when reading from an i2c EEPROM it is common to write and address, offset or index followed by a reading some values. The i915 gmbus controller provides a special "INDEX" cycle for performing

Re: [PATCH 5/7 v6] drm/i915/intel_i2c: use INDEX cycles for i2c read transactions

2012-03-29 Thread Daniel Vetter
On Thu, Mar 29, 2012 at 04:37:18PM +0800, Daniel Kurtz wrote: > On Thu, Mar 29, 2012 at 2:52 AM, Chris Wilson > wrote: > > On Thu, 29 Mar 2012 02:26:37 +0800, Daniel Kurtz > > wrote: > >> It is very common for an i2c device to require a small 1 or 2 byte write > >> followed by a read.  For exam

[PATCH 5/7 v6] drm/i915/intel_i2c: use INDEX cycles for i2c read transactions

2012-03-28 Thread Daniel Kurtz
It is very common for an i2c device to require a small 1 or 2 byte write followed by a read. For example, when reading from an i2c EEPROM it is common to write and address, offset or index followed by a reading some values. The i915 gmbus controller provides a special "INDEX" cycle for performing

[PATCH 5/7 v6] drm/i915/intel_i2c: use INDEX cycles for i2c read transactions

2012-03-28 Thread Chris Wilson
On Thu, 29 Mar 2012 02:26:37 +0800, Daniel Kurtz wrote: > It is very common for an i2c device to require a small 1 or 2 byte write > followed by a read. For example, when reading from an i2c EEPROM it is > common to write and address, offset or index followed by a reading some > values. Hmm, I

Re: [PATCH 5/7 v6] drm/i915/intel_i2c: use INDEX cycles for i2c read transactions

2012-03-28 Thread Chris Wilson
On Thu, 29 Mar 2012 02:26:37 +0800, Daniel Kurtz wrote: > It is very common for an i2c device to require a small 1 or 2 byte write > followed by a read. For example, when reading from an i2c EEPROM it is > common to write and address, offset or index followed by a reading some > values. Hmm, I h