On Fri, 2011-07-15 at 04:19 +, Matt Turner wrote:
> On Wed, Jul 13, 2011 at 6:28 AM, Benjamin Herrenschmidt
> wrote:
> > We should have a read memory barrier between reading the WPTR from
> > memory and reading ring entries based on that value (ie, we need to
> > ensure both loads are done in
On Wed, Jul 13, 2011 at 6:28 AM, Benjamin Herrenschmidt
wrote:
> We should have a read memory barrier between reading the WPTR from
> memory and reading ring entries based on that value (ie, we need to
> ensure both loads are done in order by the CPU).
>
> It could be argued that the MMIO reads in
On Fri, 2011-07-15 at 04:19 +, Matt Turner wrote:
> On Wed, Jul 13, 2011 at 6:28 AM, Benjamin Herrenschmidt
> wrote:
> > We should have a read memory barrier between reading the WPTR from
> > memory and reading ring entries based on that value (ie, we need to
> > ensure both loads are done in
On Wed, Jul 13, 2011 at 6:28 AM, Benjamin Herrenschmidt
wrote:
> We should have a read memory barrier between reading the WPTR from
> memory and reading ring entries based on that value (ie, we need to
> ensure both loads are done in order by the CPU).
>
> It could be argued that the MMIO reads in
On Wed, 2011-07-13 at 10:48 -0400, Alex Deucher wrote:
> On Wed, Jul 13, 2011 at 10:43 AM, Alex Deucher
> wrote:
> > On Wed, Jul 13, 2011 at 2:28 AM, Benjamin Herrenschmidt
> > wrote:
> >> We should have a read memory barrier between reading the WPTR from
> >> memory and reading ring entries bas
On Wed, Jul 13, 2011 at 5:42 PM, Benjamin Herrenschmidt
wrote:
> On Wed, 2011-07-13 at 10:48 -0400, Alex Deucher wrote:
>> On Wed, Jul 13, 2011 at 10:43 AM, Alex Deucher
>> wrote:
>> > On Wed, Jul 13, 2011 at 2:28 AM, Benjamin Herrenschmidt
>> > wrote:
>> >> We should have a read memory barrier
On Wed, Jul 13, 2011 at 5:42 PM, Benjamin Herrenschmidt
wrote:
> On Wed, 2011-07-13 at 10:48 -0400, Alex Deucher wrote:
>> On Wed, Jul 13, 2011 at 10:43 AM, Alex Deucher wrote:
>> > On Wed, Jul 13, 2011 at 2:28 AM, Benjamin Herrenschmidt
>> > wrote:
>> >> We should have a read memory barrier bet
We should have a read memory barrier between reading the WPTR from
memory and reading ring entries based on that value (ie, we need to
ensure both loads are done in order by the CPU).
It could be argued that the MMIO reads in r600_ack_irq() might be
enough to get that barrier but I prefer keeping
On Wed, 2011-07-13 at 10:48 -0400, Alex Deucher wrote:
> On Wed, Jul 13, 2011 at 10:43 AM, Alex Deucher wrote:
> > On Wed, Jul 13, 2011 at 2:28 AM, Benjamin Herrenschmidt
> > wrote:
> >> We should have a read memory barrier between reading the WPTR from
> >> memory and reading ring entries based
We should have a read memory barrier between reading the WPTR from
memory and reading ring entries based on that value (ie, we need to
ensure both loads are done in order by the CPU).
It could be argued that the MMIO reads in r600_ack_irq() might be
enough to get that barrier but I prefer keeping
On Wed, Jul 13, 2011 at 10:43 AM, Alex Deucher wrote:
> On Wed, Jul 13, 2011 at 2:28 AM, Benjamin Herrenschmidt
> wrote:
>> We should have a read memory barrier between reading the WPTR from
>> memory and reading ring entries based on that value (ie, we need to
>> ensure both loads are done in or
On Wed, Jul 13, 2011 at 2:28 AM, Benjamin Herrenschmidt
wrote:
> We should have a read memory barrier between reading the WPTR from
> memory and reading ring entries based on that value (ie, we need to
> ensure both loads are done in order by the CPU).
>
> It could be argued that the MMIO reads in
On Wed, Jul 13, 2011 at 10:43 AM, Alex Deucher wrote:
> On Wed, Jul 13, 2011 at 2:28 AM, Benjamin Herrenschmidt
> wrote:
>> We should have a read memory barrier between reading the WPTR from
>> memory and reading ring entries based on that value (ie, we need to
>> ensure both loads are done in or
On Wed, Jul 13, 2011 at 2:28 AM, Benjamin Herrenschmidt
wrote:
> We should have a read memory barrier between reading the WPTR from
> memory and reading ring entries based on that value (ie, we need to
> ensure both loads are done in order by the CPU).
>
> It could be argued that the MMIO reads in
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