Hi Maxime,
>> The exclusive rate code could support this if it doesn't already do so.
>> If you call clk_set_rate_exclusive(child, ) followed by
>> clk_set_rate(parent, ) the core code should try to keep the
>> child at the constant rate, or fail the clk_set_rate() call on the
>> parent. It should
Hi Stephen,
>> The idea is: if the flag is set, instead of accepting the new upstream
>> rate and recalculate the downstream rate based on a previously set
>> divider value, we change our divider value to match the same frequency
>> as before. But if we cannot, then we just keep the old way.
>>
>
On Mon, Dec 30, 2024 at 05:22:56PM -0800, Stephen Boyd wrote:
> Quoting Miquel Raynal (2024-12-23 10:43:13)
> > Hi Maxime,
> >
> > On 17/12/2024 at 13:47:53 +01, Maxime Ripard wrote:
> >
> > > On Thu, Nov 21, 2024 at 06:41:14PM +0100, Miquel Raynal wrote:
> > >> There are mainly two ways to chan
Quoting Miquel Raynal (2024-12-23 10:43:13)
> Hi Maxime,
>
> On 17/12/2024 at 13:47:53 +01, Maxime Ripard wrote:
>
> > On Thu, Nov 21, 2024 at 06:41:14PM +0100, Miquel Raynal wrote:
> >> There are mainly two ways to change a clock frequency.
> >
> > There's much more than that :)
>
> "mainly"
>
Quoting Miquel Raynal (2024-12-23 10:38:20)
> Hi Stephen,
>
> >> +/* do not passively change this clock rate during subtree rate
> >> propagation */
> >> +#define CLK_NO_RATE_CHANGE_DURING_PROPAGATION BIT(14)
> >
> > Why doesn't rate locking work?
>
> Can you be more specific? What function from
Hi Maxime,
On 17/12/2024 at 13:47:53 +01, Maxime Ripard wrote:
> On Thu, Nov 21, 2024 at 06:41:14PM +0100, Miquel Raynal wrote:
>> There are mainly two ways to change a clock frequency.
>
> There's much more than that :)
"mainly"
Or maybe I should have added "on purpose".
>
> Off the top of m
Hi Stephen,
>> +/* do not passively change this clock rate during subtree rate propagation
>> */
>> +#define CLK_NO_RATE_CHANGE_DURING_PROPAGATION BIT(14)
>
> Why doesn't rate locking work?
Can you be more specific? What function from the API is supposed to do
what I need? AFAIU, none of them is
On Thu, Nov 21, 2024 at 06:41:14PM +0100, Miquel Raynal wrote:
> There are mainly two ways to change a clock frequency.
There's much more than that :)
Off the top of my head, setting/clearing a min/max rate and changing the
parent might also result in a rate change.
And then, the firmware might
Quoting Miquel Raynal (2024-11-21 09:41:14)
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index
> adfc5bfb93b5a65b6f58c52ca2c432d651f7dd7d..94d93470479e77769e63e97462b176261103b552
> 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -1927,7 +1927,6 @@ long clk_get_accuracy(
There are mainly two ways to change a clock frequency. The active way
requires calling ->set_rate() in order to ask "on purpose" for a
frequency change. Otherwise, a clock can passively see its frequency
being updated depending on upstream clock frequency changes. In most
cases it is fine to just a
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