[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro

2014-06-12 Thread Alexandre Courbot
On Mon, Jun 9, 2014 at 7:41 PM, Alexandre Courbot wrote: > On Mon, May 19, 2014 at 6:22 PM, Lucas Stach > wrote: >> Am Montag, den 19.05.2014, 11:02 +0200 schrieb Thierry Reding: >>> On Mon, May 19, 2014 at 04:10:58PM +0900, Alexandre Courbot wrote: >>> > Some architectures (e.g. ARM) need the C

[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro

2014-06-09 Thread Alexandre Courbot
On Mon, May 19, 2014 at 6:22 PM, Lucas Stach wrote: > Am Montag, den 19.05.2014, 11:02 +0200 schrieb Thierry Reding: >> On Mon, May 19, 2014 at 04:10:58PM +0900, Alexandre Courbot wrote: >> > Some architectures (e.g. ARM) need the CPU buffers to be explicitely >> > flushed for a memory write to ta

[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro

2014-05-23 Thread Alexandre Courbot
On Mon, May 19, 2014 at 7:03 PM, Thierry Reding wrote: > On Mon, May 19, 2014 at 11:22:11AM +0200, Lucas Stach wrote: >> Am Montag, den 19.05.2014, 11:02 +0200 schrieb Thierry Reding: >> > On Mon, May 19, 2014 at 04:10:58PM +0900, Alexandre Courbot wrote: >> > > Some architectures (e.g. ARM) need

[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro

2014-05-19 Thread Alexandre Courbot
Some architectures (e.g. ARM) need the CPU buffers to be explicitely flushed for a memory write to take effect. Not doing so results in synchronization issues, especially after writing to BOs. This patch introduces a macro that flushes the caches on ARM and translates to a no-op on other architect

[Nouveau] [PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro

2014-05-19 Thread Daniel Vetter
On Mon, May 19, 2014 at 12:03:17PM +0200, Thierry Reding wrote: > On Mon, May 19, 2014 at 11:22:11AM +0200, Lucas Stach wrote: > > Am Montag, den 19.05.2014, 11:02 +0200 schrieb Thierry Reding: > > > On Mon, May 19, 2014 at 04:10:58PM +0900, Alexandre Courbot wrote: > > > > Some architectures (e.g.

[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro

2014-05-19 Thread Thierry Reding
On Mon, May 19, 2014 at 11:22:11AM +0200, Lucas Stach wrote: > Am Montag, den 19.05.2014, 11:02 +0200 schrieb Thierry Reding: > > On Mon, May 19, 2014 at 04:10:58PM +0900, Alexandre Courbot wrote: > > > Some architectures (e.g. ARM) need the CPU buffers to be explicitely > > > flushed for a memory

[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro

2014-05-19 Thread Lucas Stach
Am Montag, den 19.05.2014, 11:02 +0200 schrieb Thierry Reding: > On Mon, May 19, 2014 at 04:10:58PM +0900, Alexandre Courbot wrote: > > Some architectures (e.g. ARM) need the CPU buffers to be explicitely > > flushed for a memory write to take effect. Not doing so results in > > synchronization iss

[PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro

2014-05-19 Thread Thierry Reding
On Mon, May 19, 2014 at 04:10:58PM +0900, Alexandre Courbot wrote: > Some architectures (e.g. ARM) need the CPU buffers to be explicitely > flushed for a memory write to take effect. Not doing so results in > synchronization issues, especially after writing to BOs. It seems to me that the above is