if MT8173 display module can support 4K HDMI output,
we have to adjust VENCPLL clock from default 660MHz
to 800MHz.
Signed-off-by: Bibby Hsieh
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c |9 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h |1 +
2 files changed, 10 insertions(+)
diff --g
Hi Bibby,
Am Mittwoch, den 20.07.2016, 12:03 +0800 schrieb Bibby Hsieh:
> if MT8173 display module can support 4K HDMI output,
> we have to adjust VENCPLL clock from default 660MHz
> to 800MHz.
Is vencpll(_d2) the active source for the mm_sel mux? If so, it seems to
me that mm_sel or rather one o
