On Fri, 11 Jan 2019 14:29:28 +
Peter Rosin wrote:
> On 2019-01-10 20:25, Boris Brezillon wrote:
> > On Thu, 10 Jan 2019 18:51:21 +
> > Peter Rosin wrote:
> >
> >> On 2019-01-10 18:29, Boris Brezillon wrote:
> >>> On Thu, 10 Jan 2019 15:10:48 +
> >>> Peter Rosin wrote:
> >>>
On 2019-01-10 20:25, Boris Brezillon wrote:
> On Thu, 10 Jan 2019 18:51:21 +
> Peter Rosin wrote:
>
>> On 2019-01-10 18:29, Boris Brezillon wrote:
>>> On Thu, 10 Jan 2019 15:10:48 +
>>> Peter Rosin wrote:
>>>
The A2Q and UPDATE bits have no effect in the channel disable registers
The A2Q and UPDATE bits have no effect in the channel disable registers.
However, since they are present, assume that the intention is to disable
planes, not immediately as indicated by the RST bit, but on the next
frame shift since that is what A2Q and UPDATE means in the channel enable
registers.
On 2019-01-10 18:29, Boris Brezillon wrote:
> On Thu, 10 Jan 2019 15:10:48 +
> Peter Rosin wrote:
>
>> The A2Q and UPDATE bits have no effect in the channel disable registers.
>> However, since they are present, assume that the intention is to disable
>> planes, not immediately as indicated b
On Thu, 10 Jan 2019 18:51:21 +
Peter Rosin wrote:
> On 2019-01-10 18:29, Boris Brezillon wrote:
> > On Thu, 10 Jan 2019 15:10:48 +
> > Peter Rosin wrote:
> >
> >> The A2Q and UPDATE bits have no effect in the channel disable registers.
> >> However, since they are present, assume that
On Thu, 10 Jan 2019 15:10:48 +
Peter Rosin wrote:
> The A2Q and UPDATE bits have no effect in the channel disable registers.
> However, since they are present, assume that the intention is to disable
> planes, not immediately as indicated by the RST bit, but on the next
> frame shift since th
