[PATCH 3/6] x86: Add support for the clwb instruction

2014-11-13 Thread Ross Zwisler
On Wed, 2014-11-12 at 15:12 +0100, Borislav Petkov wrote: > On Wed, Nov 12, 2014 at 01:38:45PM +, Anvin, H Peter wrote: > > No, it doesn't. x86 requires 3.4+ at a minimum. > > The only test I see is: > > #if GCC_VERSION < 30200 > # error Sorry, your compiler is too old - please upgrade it. >

[PATCH 3/6] x86: Add support for the clwb instruction

2014-11-12 Thread Borislav Petkov
On Wed, Nov 12, 2014 at 01:38:45PM +, Anvin, H Peter wrote: > No, it doesn't. x86 requires 3.4+ at a minimum. The only test I see is: #if GCC_VERSION < 30200 # error Sorry, your compiler is too old - please upgrade it. #endif And even if we do require 3.4, the build fails with 4.1+ so... -

[PATCH 3/6] x86: Add support for the clwb instruction

2014-11-12 Thread Borislav Petkov
On Tue, Nov 11, 2014 at 11:43:13AM -0700, Ross Zwisler wrote: > +static inline void clwb(volatile void *__p) > +{ > + alternative_io_2(".byte " __stringify(NOP_DS_PREFIX) "; clflush %P0", > + ".byte 0x66; clflush %P0", > + X86_FEATURE_CLFLUSHOPT, > +

[PATCH 3/6] x86: Add support for the clwb instruction

2014-11-12 Thread Anvin, H Peter
el at lists.freedesktop.org; x86 at kernel.org Subject: Re: [PATCH 3/6] x86: Add support for the clwb instruction On Tue, Nov 11, 2014 at 11:43:13AM -0700, Ross Zwisler wrote: > +static inline void clwb(volatile void *__p) > +{ > + alternative_io_2(".byte " __stringify(NOP_D

[PATCH 3/6] x86: Add support for the clwb instruction

2014-11-11 Thread Borislav Petkov
On Tue, Nov 11, 2014 at 12:48:52PM -0700, Ross Zwisler wrote: > Essentially we need one additional byte at the beginning of the clflush so > that we can flip it into a clflushopt by changing that byte into a 0x66 > prefix. Two options are to either insert a 1 byte ASM_NOP1, or to add a 1 > byte NO

[PATCH 3/6] x86: Add support for the clwb instruction

2014-11-11 Thread Borislav Petkov
On Tue, Nov 11, 2014 at 12:40:00PM -0700, Ross Zwisler wrote: > Yep, it's weird, I know. :) But sure, saving opcode space, makes sense to me. Btw, I'd still be interested about this: > +static inline void clwb(volatile void *__p) > +{ > + alternative_io_2(".byte " __stringify(NOP_DS_PREFIX)

[PATCH 3/6] x86: Add support for the clwb instruction

2014-11-11 Thread Borislav Petkov
On Tue, Nov 11, 2014 at 08:12:39PM +0100, Borislav Petkov wrote: > > +".byte 0x66; xsaveopt %P0", > > Huh, XSAVEOPT?!? Shouldn't that be CLWB?? Bah, the same opcodes, only 0x66 prefix makes it into CLWB. Could use a comment I guess. -- Regards/Gruss, Boris. Sent from a

[PATCH 3/6] x86: Add support for the clwb instruction

2014-11-11 Thread Borislav Petkov
On Tue, Nov 11, 2014 at 11:43:13AM -0700, Ross Zwisler wrote: > Add support for the new clwb instruction. This instruction was > announced in the document "Intel Architecture Instruction Set Extensions > Programming Reference" with reference number 319433-022. > > https://software.intel.com/sites

[PATCH 3/6] x86: Add support for the clwb instruction

2014-11-11 Thread Ross Zwisler
On Tue, 2014-11-11 at 20:46 +0100, Borislav Petkov wrote: > On Tue, Nov 11, 2014 at 12:40:00PM -0700, Ross Zwisler wrote: > > Yep, it's weird, I know. :) > > But sure, saving opcode space, makes sense to me. > > Btw, I'd still be interested about this: > > > +static inline void clwb(volatile vo

[PATCH 3/6] x86: Add support for the clwb instruction

2014-11-11 Thread Ross Zwisler
On Tue, 2014-11-11 at 20:12 +0100, Borislav Petkov wrote: > On Tue, Nov 11, 2014 at 11:43:13AM -0700, Ross Zwisler wrote: > > Add support for the new clwb instruction. This instruction was > > announced in the document "Intel Architecture Instruction Set Extensions > > Programming Reference" with

[PATCH 3/6] x86: Add support for the clwb instruction

2014-11-11 Thread Ross Zwisler
On Tue, 2014-11-11 at 20:19 +0100, Borislav Petkov wrote: > On Tue, Nov 11, 2014 at 08:12:39PM +0100, Borislav Petkov wrote: > > > + ".byte 0x66; xsaveopt %P0", > > > > Huh, XSAVEOPT?!? Shouldn't that be CLWB?? > > Bah, the same opcodes, only 0x66 prefix makes it into CLWB. Could

[PATCH 3/6] x86: Add support for the clwb instruction

2014-11-11 Thread Ross Zwisler
Add support for the new clwb instruction. This instruction was announced in the document "Intel Architecture Instruction Set Extensions Programming Reference" with reference number 319433-022. https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf Here are some things of not