On 5/7/2025 11:18 PM, Krzysztof Kozlowski wrote:
On 23/04/2025 04:46, Abhinav Kumar wrote:
Hi Krzysztof
On 12/3/2024 12:04 AM, Krzysztof Kozlowski wrote:
On 03/12/2024 04:31, Abhinav Kumar wrote:
On some chipsets the display port controller can support more
Which chipsets?
From the
On 4/23/2025 7:23 AM, Dmitry Baryshkov wrote:
On Tue, Apr 22, 2025 at 07:46:57PM -0700, Abhinav Kumar wrote:
On 12/3/2024 5:43 AM, Dmitry Baryshkov wrote:
On Mon, Dec 02, 2024 at 07:31:41PM -0800, Abhinav Kumar wrote:
On some chipsets the display port controller can support more
than one
On 23/04/2025 04:46, Abhinav Kumar wrote:
> Hi Krzysztof
>
> On 12/3/2024 12:04 AM, Krzysztof Kozlowski wrote:
>> On 03/12/2024 04:31, Abhinav Kumar wrote:
>>> On some chipsets the display port controller can support more
>>
>> Which chipsets?
>>
>
> From the current list of chipsets which suppo
On Tue, Apr 22, 2025 at 07:46:57PM -0700, Abhinav Kumar wrote:
>
>
> On 12/3/2024 5:43 AM, Dmitry Baryshkov wrote:
> > On Mon, Dec 02, 2024 at 07:31:41PM -0800, Abhinav Kumar wrote:
> > > On some chipsets the display port controller can support more
> > > than one pixel stream (multi-stream trans
On 12/3/2024 5:43 AM, Dmitry Baryshkov wrote:
On Mon, Dec 02, 2024 at 07:31:41PM -0800, Abhinav Kumar wrote:
On some chipsets the display port controller can support more
than one pixel stream (multi-stream transport). To support MST
on such chipsets, add the binding for stream 1 pixel clock
Hi Krzysztof
On 12/3/2024 12:04 AM, Krzysztof Kozlowski wrote:
On 03/12/2024 04:31, Abhinav Kumar wrote:
On some chipsets the display port controller can support more
Which chipsets?
From the current list of chipsets which support DP, the following can
support more than one stream.
qcom
On Mon, Dec 02, 2024 at 07:31:41PM -0800, Abhinav Kumar wrote:
> On some chipsets the display port controller can support more
> than one pixel stream (multi-stream transport). To support MST
> on such chipsets, add the binding for stream 1 pixel clock for
> display port controller. Since this mode
On 03/12/2024 04:31, Abhinav Kumar wrote:
> On some chipsets the display port controller can support more
Which chipsets?
> than one pixel stream (multi-stream transport). To support MST
> on such chipsets, add the binding for stream 1 pixel clock for
> display port controller. Since this mode is
On some chipsets the display port controller can support more
than one pixel stream (multi-stream transport). To support MST
on such chipsets, add the binding for stream 1 pixel clock for
display port controller. Since this mode is not supported on all
chipsets, add exception rules and min/max item
