On 10.03.2017 05:32, Sean Paul wrote:
> From: zain wang
>
> There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg
> list. We should use BIT_4 in ANALOGIX_DP_PD to control the pll power
> instead of ANALOGIX_DP_PLL_CTL.
>
> Cc: Douglas Anderson
> Signed-off-by: zain wang
> Signe
From: zain wang
There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg
list. We should use BIT_4 in ANALOGIX_DP_PD to control the pll power
instead of ANALOGIX_DP_PLL_CTL.
Cc: Douglas Anderson
Signed-off-by: zain wang
Signed-off-by: Sean Paul
---
drivers/gpu/drm/bridge/analo