[PATCH 2/8 v7] drm/i915/intel_i2c: use double-buffered writes

2012-03-30 Thread Daniel Kurtz
The GMBUS controller GMBUS3 register is double-buffered. Take advantage of this by writing two 4-byte words before the first wait for HW_RDY. This helps keep the GMBUS controller from becoming idle during long writes. In fact, during experiments using the GMBUS interrupts, the HW_RDY interrupt w

[PATCH 2/8 v7] drm/i915/intel_i2c: use double-buffered writes

2012-03-30 Thread Daniel Kurtz
The GMBUS controller GMBUS3 register is double-buffered. Take advantage of this by writing two 4-byte words before the first wait for HW_RDY. This helps keep the GMBUS controller from becoming idle during long writes. In fact, during experiments using the GMBUS interrupts, the HW_RDY interrupt w