[Intel-gfx] [PATCH 2/2] intel: Detect cache domain inconsistency with valgrind

2012-02-09 Thread Daniel Vetter
On Thu, Feb 09, 2012 at 10:43:11AM +, Chris Wilson wrote: > Every access to either the GTT or CPU pointer is supposed to be > proceeded by a set_domain ioctl so that GEM is able to manage the cache > domains correctly and for the following access to be coherent. Of > course, some people explici

[PATCH 2/2] intel: Detect cache domain inconsistency with valgrind

2012-02-09 Thread Chris Wilson
Every access to either the GTT or CPU pointer is supposed to be proceeded by a set_domain ioctl so that GEM is able to manage the cache domains correctly and for the following access to be coherent. Of course, some people explicitly want incoherent, non-blocking access which is going to trigger war

Re: [Intel-gfx] [PATCH 2/2] intel: Detect cache domain inconsistency with valgrind

2012-02-09 Thread Daniel Vetter
On Thu, Feb 09, 2012 at 10:43:11AM +, Chris Wilson wrote: > Every access to either the GTT or CPU pointer is supposed to be > proceeded by a set_domain ioctl so that GEM is able to manage the cache > domains correctly and for the following access to be coherent. Of > course, some people explici

[PATCH 2/2] intel: Detect cache domain inconsistency with valgrind

2012-02-09 Thread Chris Wilson
Every access to either the GTT or CPU pointer is supposed to be proceeded by a set_domain ioctl so that GEM is able to manage the cache domains correctly and for the following access to be coherent. Of course, some people explicitly want incoherent, non-blocking access which is going to trigger war