On 2/12/21 9:43 AM, Linus Walleij wrote:
On Thu, Feb 4, 2021 at 11:05 PM Marek Vasut wrote:
On 2/4/21 10:10 PM, Doug Anderson wrote:
+ /*
+* Reset the chip, pull EN line low for t_reset=10ms,
+* then high for t_en=1ms.
+*/
+ gpiod_set_value(ctx->enable_gpi
On Thu, Feb 4, 2021 at 11:05 PM Marek Vasut wrote:
> On 2/4/21 10:10 PM, Doug Anderson wrote:
> + /*
> +* Reset the chip, pull EN line low for t_reset=10ms,
> +* then high for t_en=1ms.
> +*/
> + gpiod_set_value(ctx->enable_gpio, 0);
>
On 2/4/21 10:10 PM, Doug Anderson wrote:
Hi,
Hi,
[...]
+ regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
Do you need to list REG_RC_RESET as volatile? Specifically you need
to make sure it's not cached...
Isn't volatile table exactly for this purpose -- to make sure the reg is
not c
Hi,
On Thu, Feb 4, 2021 at 10:41 AM Marek Vasut wrote:
>
> >> +static const struct regmap_range sn65dsi83_volatile_ranges[] = {
> >> + regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL),
> >
> > Why is REG_RC_LVDS_PLL volatile?
>
> See register 0xa bit 7, PLL_EN_STAT .
Wow, I looked at it
On 2/4/21 6:15 PM, Doug Anderson wrote:
Hi,
[...]
+static const struct regmap_range sn65dsi83_volatile_ranges[] = {
+ regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL),
Why is REG_RC_LVDS_PLL volatile?
See register 0xa bit 7, PLL_EN_STAT .
+ regmap_reg_range(REG_IRQ_STAT, R
Hi,
On Sat, Jan 30, 2021 at 10:10 AM Marek Vasut wrote:
>
> Add driver for TI SN65DSI83 Single-Channel DSI to Single-Link LVDS bridge.
> The driver operates the chip over I2C bus. Currently the LVDS clock are
> always derived from DSI clock lane, which is the usual mode of operation,
> support fo
Add driver for TI SN65DSI83 Single-Channel DSI to Single-Link LVDS bridge.
The driver operates the chip over I2C bus. Currently the LVDS clock are
always derived from DSI clock lane, which is the usual mode of operation,
support for clock from external oscillator is not implemented, but it is
easy
