On Sat, Jun 3, 2017 at 3:38 AM, Maxime Ripard
wrote:
> On Fri, Jun 02, 2017 at 06:10:18PM +0800, Chen-Yu Tsai wrote:
>> The HDMI controller found in earlier Allwinner SoCs have slight
>> differences:
>>
>> - Need different initial values for the PLL related registers
>>
>> - Different behavior
The HDMI controller found in earlier Allwinner SoCs have slight
differences:
- Need different initial values for the PLL related registers
- Different behavior of the DDC and TMDS clocks
- Different register layout for the DDC portion
- Separate DDC parent clock on the A31
- Explicit
On Fri, Jun 02, 2017 at 06:10:18PM +0800, Chen-Yu Tsai wrote:
> The HDMI controller found in earlier Allwinner SoCs have slight
> differences:
>
> - Need different initial values for the PLL related registers
>
> - Different behavior of the DDC and TMDS clocks
>
> - Different register layo