Re: [Freedreno] [PATCH 1/3] drm/msm/mdp5: Configure PP_SYNC_HEIGHT to double the vtotal

Hi Abhinav, Angelo, Rob, On 4/9/21 2:08 AM, Rob Clark wrote: On Thu, Apr 8, 2021 at 4:16 PM AngeloGioacchino Del Regno wrote: Il gio 8 apr 2021, 21:05 Rob Clark ha scritto: On Wed, Apr 7, 2021 at 12:11 PM AngeloGioacchino Del Regno wrote: Il 07/04/21 20:19, abhin...@codeaurora.org ha s

Re: [Freedreno] [PATCH 1/3] drm/msm/mdp5: Configure PP_SYNC_HEIGHT to double the vtotal

On Thu, Apr 8, 2021 at 4:16 PM AngeloGioacchino Del Regno wrote: > > > Il gio 8 apr 2021, 21:05 Rob Clark ha scritto: >> >> On Wed, Apr 7, 2021 at 12:11 PM AngeloGioacchino Del Regno >> wrote: >> > >> > Il 07/04/21 20:19, abhin...@codeaurora.org ha scritto: >> > > Hi Marijn >> > > >> > > On 2021

Re: [Freedreno] [PATCH 1/3] drm/msm/mdp5: Configure PP_SYNC_HEIGHT to double the vtotal

Il gio 8 apr 2021, 21:05 Rob Clark ha scritto: > On Wed, Apr 7, 2021 at 12:11 PM AngeloGioacchino Del Regno > wrote: > > > > Il 07/04/21 20:19, abhin...@codeaurora.org ha scritto: > > > Hi Marijn > > > > > > On 2021-04-06 14:47, Marijn Suijten wrote: > > >> Leaving this at a close-to-maximum reg

Re: [Freedreno] [PATCH 1/3] drm/msm/mdp5: Configure PP_SYNC_HEIGHT to double the vtotal

On Wed, Apr 7, 2021 at 12:11 PM AngeloGioacchino Del Regno wrote: > > Il 07/04/21 20:19, abhin...@codeaurora.org ha scritto: > > Hi Marijn > > > > On 2021-04-06 14:47, Marijn Suijten wrote: > >> Leaving this at a close-to-maximum register value 0xFFF0 means it takes > >> very long for the MDSS to

Re: [Freedreno] [PATCH 1/3] drm/msm/mdp5: Configure PP_SYNC_HEIGHT to double the vtotal

Il 07/04/21 20:19, abhin...@codeaurora.org ha scritto: Hi Marijn On 2021-04-06 14:47, Marijn Suijten wrote: Leaving this at a close-to-maximum register value 0xFFF0 means it takes very long for the MDSS to generate a software vsync interrupt when the hardware TE interrupt doesn't arrive.  Confi

Re: [Freedreno] [PATCH 1/3] drm/msm/mdp5: Configure PP_SYNC_HEIGHT to double the vtotal

Hi Marijn On 2021-04-06 14:47, Marijn Suijten wrote: Leaving this at a close-to-maximum register value 0xFFF0 means it takes very long for the MDSS to generate a software vsync interrupt when the hardware TE interrupt doesn't arrive. Configuring this to double the vtotal (like some downstream k

[PATCH 1/3] drm/msm/mdp5: Configure PP_SYNC_HEIGHT to double the vtotal

Leaving this at a close-to-maximum register value 0xFFF0 means it takes very long for the MDSS to generate a software vsync interrupt when the hardware TE interrupt doesn't arrive. Configuring this to double the vtotal (like some downstream kernels) leads to a frame to take at most twice before th