Re: [PATCH 1/2] drm: bridge: tc358767: increase PLL lock time delay

2023-07-08 Thread Marek Vasut
On 6/2/23 21:15, Lucas Stach wrote: From: David Jander The PLL often fails to lock with this delay. The new value was determined by trial and error increasing the delay bit by bit until the error did not occurr anymore even after several tries. Then double that value was taken as the minimum de

Re: [PATCH 1/2] drm: bridge: tc358767: increase PLL lock time delay

2023-06-02 Thread Marek Vasut
On 6/2/23 21:15, Lucas Stach wrote: From: David Jander The PLL often fails to lock with this delay. The new value was determined by trial and error increasing the delay bit by bit until the error did not occurr anymore even after several tries. Then double that value was taken as the minimum de

[PATCH 1/2] drm: bridge: tc358767: increase PLL lock time delay

2023-06-02 Thread Lucas Stach
From: David Jander The PLL often fails to lock with this delay. The new value was determined by trial and error increasing the delay bit by bit until the error did not occurr anymore even after several tries. Then double that value was taken as the minimum delay to be safe. Signed-off-by: David