Hi Dale,
thanks for looking into this patch,
> > + /*
> > +* i915->gt[0] == &i915->gt0
> > +*/
> > +#define I915_MAX_GT 4
> > + struct intel_gt *gt[I915_MAX_GT];
> > +
>
>
> It would be nice if I915_MAX_GT was defined in a more basic header file so
> that the definition of I915_MAX_
Hi Andi,
On 2022-01-11 14:15:51, Andi Shyti wrote:
>
> From: Tvrtko Ursulin
>
> On a multi-tile platform, each tile has its own registers + GGTT
> space, and BAR 0 is extended to cover all of them.
>
> Up to four gts are supported in i915->gt[], with slot zero
> shadowing the existing i915->gt
From: Tvrtko Ursulin
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four gts are supported in i915->gt[], with slot zero
shadowing the existing i915->gt0 to enable source compatibility
with legacy driver paths. A for_each
