Re: [PATCH 09/20] drm/bridge: tc358775: remove complex vsdelay calculation

2024-09-08 Thread Daniel Semkowicz
On Fri, Sep 6, 2024 at 4:34 PM Michael Walle wrote: > > Hi Daniel, > > > > To cite the datasheet on VSDELAY: > > > During DSI link speed is slower than that of LVDS link’s, data needs > > > to be buffer within 775XBG before outputting to prevent data from > > > underflow. Register field VPCT

Re: [PATCH 09/20] drm/bridge: tc358775: remove complex vsdelay calculation

2024-09-06 Thread Michael Walle
Hi Daniel, > > To cite the datasheet on VSDELAY: > > During DSI link speed is slower than that of LVDS link’s, data needs > > to be buffer within 775XBG before outputting to prevent data from > > underflow. Register field VPCTRL[VSDELAY] is used to for this purpose > > > > This driver assume

Re: [PATCH 09/20] drm/bridge: tc358775: remove complex vsdelay calculation

2024-09-06 Thread Daniel Semkowicz
Hello Michael, On Mon, May 6, 2024 at 3:35 PM Michael Walle wrote: > > To cite the datasheet on VSDELAY: > During DSI link speed is slower than that of LVDS link’s, data needs > to be buffer within 775XBG before outputting to prevent data from > underflow. Register field VPCTRL[VSDELAY] is

[PATCH 09/20] drm/bridge: tc358775: remove complex vsdelay calculation

2024-05-06 Thread Michael Walle
To cite the datasheet on VSDELAY: During DSI link speed is slower than that of LVDS link’s, data needs to be buffer within 775XBG before outputting to prevent data from underflow. Register field VPCTRL[VSDELAY] is used to for this purpose This driver assumes that the DSI link speed is the pi