The GMBUS controller GMBUS3 register is double-buffered. Take advantage
of this by writing two 4-byte words before the first wait for HW_RDY.
This helps keep the GMBUS controller from becoming idle during long writes.
Signed-off-by: Daniel Kurtz
---
drivers/gpu/drm/i915/intel_i2c.c | 14
The GMBUS controller GMBUS3 register is double-buffered. Take advantage
of this by writing two 4-byte words before the first wait for HW_RDY.
This helps keep the GMBUS controller from becoming idle during long writes.
Signed-off-by: Daniel Kurtz
---
drivers/gpu/drm/i915/intel_i2c.c | 14
On Wed, 28 Mar 2012 02:36:18 +0800, Daniel Kurtz
wrote:
> @@ -276,6 +269,13 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv,
> struct i2c_msg *msg,
>
> I915_WRITE(GMBUS3 + reg_offset, val);
> POSTING_READ(GMBUS2 + reg_offset);
You might as well squash this po
On Wed, 28 Mar 2012 02:36:18 +0800, Daniel Kurtz wrote:
> @@ -276,6 +269,13 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv,
> struct i2c_msg *msg,
>
> I915_WRITE(GMBUS3 + reg_offset, val);
> POSTING_READ(GMBUS2 + reg_offset);
You might as well squash this pos
