On Fri, Nov 13, 2015 at 04:08:53PM +0800, Chen-Yu Tsai wrote:
> On Mon, Nov 9, 2015 at 12:18 PM, Chen-Yu Tsai wrote:
> > On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard
> > wrote:
> >> The Allwinner SoCs have a gate controller to gate the access to the DRAM
> >> clock to the some devices that nee
On Mon, Nov 9, 2015 at 12:18 PM, Chen-Yu Tsai wrote:
> On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard
> wrote:
>> The Allwinner SoCs have a gate controller to gate the access to the DRAM
>> clock to the some devices that need to access the DRAM directly (mostly
>> display / image related IPs).
>
On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard
wrote:
> The Allwinner SoCs have a gate controller to gate the access to the DRAM
> clock to the some devices that need to access the DRAM directly (mostly
> display / image related IPs).
>
> Use a simple gates driver to support it.
>
> Signed-off-by
The Allwinner SoCs have a gate controller to gate the access to the DRAM
clock to the some devices that need to access the DRAM directly (mostly
display / image related IPs).
Use a simple gates driver to support it.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi/clk-simple-gates.c | 2 ++
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