On 10/15/2015 02:05 AM, Stephen Boyd wrote:
> On 10/14, Archit Taneja wrote:
>> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
>> b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
>> new file mode 100644
>> index 000..e71b4ee
>> --- /dev/null
>> +++ b/drivers/gpu/drm/msm/dsi/pl
On 10/16, Archit Taneja wrote:
>
>
> On 10/15/2015 02:05 AM, Stephen Boyd wrote:
> >On 10/14, Archit Taneja wrote:
> >>+ bytediv->hw.init = &bytediv_init;
> >>+ bytediv->reg = pll_28nm->mmio + REG_DSI_28nm_8960_PHY_PLL_CTRL_9;
> >>+
> >>+ snprintf(parent, 32, "dsi%dvco_clk", pll_28nm->id);
Add DSI PLL common clock framework clocks for 8960 PHY.
The PLL here is different from the ones found in B family msm chips. As
before, the DSI provides two clocks to the outside world. dsixpll and
dsixpllbyte (x = 1, 2). dsixpll is a regular clock divider, but
dsixpllbyte is modelled as a custom
On 10/14, Archit Taneja wrote:
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
> b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
> new file mode 100644
> index 000..e71b4ee
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
> @@ -0,0 +1,529 @@
> +/*
> + *
