On Fri, Dec 13, 2019 at 07:10:41PM +0100, Miquel Raynal wrote:
> PX30 SoCs use a single PHY shared by two display pipelines: MIPI DSI
> and LVDS. In the case of the LVDS IP, document the possibility to fill
> a PHY handle.
>
> Signed-off-by: Miquel Raynal
> ---
> .../devicetree/bindings/display/r
PX30 SoCs use a single PHY shared by two display pipelines: MIPI DSI
and LVDS. In the case of the LVDS IP, document the possibility to fill
a PHY handle.
Signed-off-by: Miquel Raynal
---
.../devicetree/bindings/display/rockchip/rockchip-lvds.txt | 3 +++
1 file changed, 3 insertions(+)
diff
