[PATCH] video: drm: exynos: mie bypass enable for fimd

2012-12-28 Thread Inki Dae
2012/12/28 Leela Krishna Amudala : > Hello Inki Dae, > > On Thu, Dec 27, 2012 at 11:47 AM, Inki Dae wrote: >> >> Hi, >> >> DISP1BLK_CFG register is related to GScaler, HDCP and MIXER as well. So >> it's not good that this register is controlled in fimd module. And I think >> the function to contro

[PATCH] video: drm: exynos: mie bypass enable for fimd

2012-12-28 Thread Leela Krishna Amudala
Hello Inki Dae, On Thu, Dec 27, 2012 at 11:47 AM, Inki Dae wrote: > > Hi, > > DISP1BLK_CFG register is related to GScaler, HDCP and MIXER as well. So > it's not good that this register is controlled in fimd module. And I think > the function to control the register should be placed in SoC common

Re: [PATCH] video: drm: exynos: mie bypass enable for fimd

2012-12-27 Thread Inki Dae
2012/12/28 Leela Krishna Amudala : > Hello Inki Dae, > > On Thu, Dec 27, 2012 at 11:47 AM, Inki Dae wrote: >> >> Hi, >> >> DISP1BLK_CFG register is related to GScaler, HDCP and MIXER as well. So >> it's not good that this register is controlled in fimd module. And I think >> the function to contro

Re: [PATCH] video: drm: exynos: mie bypass enable for fimd

2012-12-27 Thread Leela Krishna Amudala
Hello Inki Dae, On Thu, Dec 27, 2012 at 11:47 AM, Inki Dae wrote: > > Hi, > > DISP1BLK_CFG register is related to GScaler, HDCP and MIXER as well. So > it's not good that this register is controlled in fimd module. And I think > the function to control the register should be placed in SoC common

[PATCH] video: drm: exynos: mie bypass enable for fimd

2012-12-27 Thread Inki Dae
Hi, DISP1BLK_CFG register is related to GScaler, HDCP and MIXER as well. So it's not good that this register is controlled in fimd module. And I think the function to control the register should be placed in SoC common file . In other words, other drivers should be able to control the register thr

Re: [PATCH] video: drm: exynos: mie bypass enable for fimd

2012-12-26 Thread Inki Dae
Hi, DISP1BLK_CFG register is related to GScaler, HDCP and MIXER as well. So it's not good that this register is controlled in fimd module. And I think the function to control the register should be placed in SoC common file . In other words, other drivers should be able to control the register thr

[PATCH] video: drm: exynos: mie bypass enable for fimd

2012-12-26 Thread Leela Krishna Amudala
Bypasses the mie for fimd by parsing the register and bit offset values from "mie-bypass" node, if "mie-bypass" node is present in the dts file. Signed-off-by: Leela Krishna Amudala --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 55 1 file changed, 55 insertions(

[PATCH] video: drm: exynos: mie bypass enable for fimd

2012-12-26 Thread Leela Krishna Amudala
Bypasses the mie for fimd by parsing the register and bit offset values from "mie-bypass" node, if "mie-bypass" node is present in the dts file. Signed-off-by: Leela Krishna Amudala --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 55 1 file changed, 55 insertions(