On 2014.12.18 12:12:33 -0600, jeff.mcgee at intel.com wrote:
> diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
> index 15dd01d..be38adf 100644
> --- a/include/drm/i915_drm.h
> +++ b/include/drm/i915_drm.h
> @@ -340,6 +340,10 @@ typedef struct drm_i915_irq_wait {
> #define I915_PARAM_H
On Fri, Jan 09, 2015 at 10:56:16AM +0800, Zhenyu Wang wrote:
> On 2014.12.18 12:12:33 -0600, jeff.mcgee at intel.com wrote:
> > diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
> > index 15dd01d..be38adf 100644
> > --- a/include/drm/i915_drm.h
> > +++ b/include/drm/i915_drm.h
> > @@ -34
Link to the archived drm/i915 patches corresponding to this change:
http://lists.freedesktop.org/archives/intel-gfx/2014-December/057817.html
From: Jeff McGee
Update kernel interface with new I915_GETPARAM ioctl entries for
slice total, subslice total, EU total, and threads per EU. Add a
wrapping function for each parameter.
The motivation for this change is that fusing can be used to create
multiple slice, subslice, and EU configurat
From: Jeff McGee
The motivation for this change is that fusing can be used to create
multiple slice, subslice, and EU configuration within the same PCI
ID. CHV is the first such device to do this and thus make an ID-based
lookup table approach unreliable. The best solution is for the kernel
to de
