[Intel-gfx] [PATCH] intel: Detect cache domain inconsistency with valgrind

2012-02-11 Thread Daniel Vetter
On Sat, Feb 11, 2012 at 11:47:36AM +, Chris Wilson wrote: > Every access to either the GTT or CPU pointer is supposed to be > proceeded by a set_domain ioctl so that GEM is able to manage the cache > domains correctly and for the following access to be coherent. Of > course, some people explici

[PATCH] intel: Detect cache domain inconsistency with valgrind

2012-02-11 Thread Chris Wilson
Every access to either the GTT or CPU pointer is supposed to be proceeded by a set_domain ioctl so that GEM is able to manage the cache domains correctly and for the following access to be coherent. Of course, some people explicitly want incoherent, non-blocking access which is going to trigger war

Re: [Intel-gfx] [PATCH] intel: Detect cache domain inconsistency with valgrind

2012-02-11 Thread Daniel Vetter
On Sat, Feb 11, 2012 at 11:47:36AM +, Chris Wilson wrote: > Every access to either the GTT or CPU pointer is supposed to be > proceeded by a set_domain ioctl so that GEM is able to manage the cache > domains correctly and for the following access to be coherent. Of > course, some people explici

[PATCH] intel: Detect cache domain inconsistency with valgrind

2012-02-11 Thread Chris Wilson
Every access to either the GTT or CPU pointer is supposed to be proceeded by a set_domain ioctl so that GEM is able to manage the cache domains correctly and for the following access to be coherent. Of course, some people explicitly want incoherent, non-blocking access which is going to trigger war