On Tue, 2017-05-02 at 17:38 +0200, Lucas Stach wrote:
> By setting the SFTRST bit, the PRE will be held in the lowest power state
> with clocks to the internal blocks gated. When external clock gating is
> used (from the external clock controller, or by setting the CLKGATE bit)
> the PRE will spora
By setting the SFTRST bit, the PRE will be held in the lowest power state
with clocks to the internal blocks gated. When external clock gating is
used (from the external clock controller, or by setting the CLKGATE bit)
the PRE will sporadically fail to start.
Signed-off-by: Lucas Stach
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