On Mon, 2019-01-07 at 12:58 +0100, Lucas Stach wrote:
> Am Freitag, den 21.12.2018, 12:11 +0100 schrieb Philipp Zabel:
> > Hi Lucas,
> >
> > > On Wed, Dec 19, 2018 at 4:40 PM Lucas Stach
> > > wrote:
> > >
> > > On a NOP double buffer update where current buffer address is the same
> > > as the
Am Freitag, den 21.12.2018, 12:11 +0100 schrieb Philipp Zabel:
> Hi Lucas,
>
> > On Wed, Dec 19, 2018 at 4:40 PM Lucas Stach wrote:
> >
> > On a NOP double buffer update where current buffer address is the same
> > as the next buffer address, the SDW_UPDATE bit clears too late.
>
> What does th
Hi Lucas,
On Wed, Dec 19, 2018 at 4:40 PM Lucas Stach wrote:
>
> On a NOP double buffer update where current buffer address is the same
> as the next buffer address, the SDW_UPDATE bit clears too late.
What does this mean, exactly? Does the hardware behave differently
if the writel to IPU_PRE_NE
On a NOP double buffer update where current buffer address is the same
as the next buffer address, the SDW_UPDATE bit clears too late. As we
are now using this bit to determine when it is safe to signal flip
completion to userspace this will delay completion of atomic commits
where one plane doesn'
