This is a note to let you know that I've just added the patch titled
drm/xe: Use write-back caching mode for system memory on DGFX
to the 6.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch i
The caching mode for buffer objects with VRAM as a possible placement was
forced to write-combined, regardless of placement.
However, write-combined system memory is expensive to allocate and even though
it is pooled, the pool is expensive to shrink, since it involves global CPU TLB
flushes.
M
On Wed, Jun 19, 2024 at 06:39:04PM +0200, Thomas Hellström wrote:
> The caching mode for buffer objects with VRAM as a possible
> placement was forced to write-combined, regardless of placement.
>
> However, write-combined system memory is expensive to allocate and
> even though it is pooled, the
On Wed, 2024-06-19 at 18:39 +0200, Thomas Hellström wrote:
> The caching mode for buffer objects with VRAM as a possible
> placement was forced to write-combined, regardless of placement.
>
> However, write-combined system memory is expensive to allocate and
> even though it is pooled, the pool is
On Wed, Jun 19, 2024 at 06:39:04PM +0200, Thomas Hellström wrote:
> The caching mode for buffer objects with VRAM as a possible
> placement was forced to write-combined, regardless of placement.
>
> However, write-combined system memory is expensive to allocate and
> even though it is pooled, the
On 19/06/2024 17:39, Thomas Hellström wrote:
The caching mode for buffer objects with VRAM as a possible
placement was forced to write-combined, regardless of placement.
However, write-combined system memory is expensive to allocate and
even though it is pooled, the pool is expensive to shrink,
The caching mode for buffer objects with VRAM as a possible
placement was forced to write-combined, regardless of placement.
However, write-combined system memory is expensive to allocate and
even though it is pooled, the pool is expensive to shrink, since
it involves global CPU TLB flushes.
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