lt;mailto:amd-...@lists.freedesktop.org>;
> > dri-devel@lists.freedesktop.org
> > <mailto:dri-devel@lists.freedesktop.org>; Daniel Vetter
> > <mailto:dan...@ffwll.ch>; Dave Airlie
> > <mailto:airl...@redhat.com>; Thomas Hellström
>
If tbo.mem.bus.caching is cached, buffer is intended to be mapped
as cached from CPU. Map it with ioremap_cache.
This wasn't necessary before as device memory was never mapped
as cached from CPU side. It becomes necessary for aldebaran as
device memory is mapped cached from CPU.
Signed-off-by: Oa
Hi Oak,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip linus/master v5.12-rc1 next-20210304]
[cannot apply to tegra-drm/drm/tegra/for-next drm-exynos/exynos-drm-next
drm/drm-next]
[If your patch is
Hi Oak,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip linus/master v5.12-rc1 next-20210304]
[cannot apply to tegra-drm/drm/tegra/for-next drm-exynos/exynos-drm-next
drm/drm-next]
[If your patch is
Am 04.03.21 um 18:40 schrieb Bhardwaj, Rajneesh:
On 3/4/2021 12:31 PM, Christian König wrote:
[CAUTION: External Email]
Am 04.03.21 um 18:01 schrieb Bhardwaj, Rajneesh:
I was wondering if a managed version of such API exists but looks like
none. We only have devm_ioremap_wc but that is vali
On 3/4/2021 12:31 PM, Christian König wrote:
[CAUTION: External Email]
Am 04.03.21 um 18:01 schrieb Bhardwaj, Rajneesh:
I was wondering if a managed version of such API exists but looks like
none. We only have devm_ioremap_wc but that is valid only for
PAGE_CACHE_MODE_WC whereas ioremap_cache
Am 04.03.21 um 18:01 schrieb Bhardwaj, Rajneesh:
I was wondering if a managed version of such API exists but looks like
none. We only have devm_ioremap_wc but that is valid only for
PAGE_CACHE_MODE_WC whereas ioremap_cache uses _WB. One more small
comment below.
Acked-by: Rajneesh Bhardwaj
I was wondering if a managed version of such API exists but looks like
none. We only have devm_ioremap_wc but that is valid only for
PAGE_CACHE_MODE_WC whereas ioremap_cache uses _WB. One more small
comment below.
Acked-by: Rajneesh Bhardwaj
On 3/4/2021 11:04 AM, Oak Zeng wrote:
If tbo.mem
If tbo.mem.bus.caching is cached, buffer is intended to be mapped
as cached from CPU. Map it with ioremap_cache.
This wasn't necessary before as device memory was never mapped
as cached from CPU side. It becomes necessary for aldebaran as
device memory is mapped cached from CPU.
Signed-off-by: Oa
I think we should check for CONFIG_X86 instead, but in general it sounds
like the right approach to me for now.
Regards,
Christian.
Am 03.03.21 um 22:12 schrieb Oak Zeng:
If tbo.mem.bus.caching is cached, buffer is intended to be mapped
as cached from CPU. Map it with ioremap_cache.
This wasn
aniel Vetter ; Dave
Airlie ; Thomas Hellström (Intel)
; dan.j.willi...@intel.com
*Cc:* kbuild-...@lists.01.org; Kuehling, Felix
; Kasiviswanathan, Harish
; Deucher, Alexander
; Huang, JinHuiEric
; Koenig, Christian
*Subject:* Re: [PATCH] drm/ttm: ioremap buffer according to TTM mem
caching se
If tbo.mem.bus.caching is cached, buffer is intended to be mapped
as cached from CPU. Map it with ioremap_cache.
This wasn't necessary before as device memory was never mapped
as cached from CPU side. It becomes necessary for aldebaran as
device memory is mapped cached from CPU.
Signed-off-by: Oa
ucher, Alexander
; Huang, JinHuiEric ;
Koenig, Christian
Subject: Re: [PATCH] drm/ttm: ioremap buffer according to TTM mem caching
setting
Hi Oak,
config: parisc-randconfig-r012-20210302 (attached as .config)
It's not the Intel driver build which fails here, but the build bot is just
1.org; Kuehling,
Felix ; Kasiviswanathan, Harish
; Deucher, Alexander
; Huang, JinHuiEric
; Koenig, Christian
*Subject:* Re: [PATCH] drm/ttm: ioremap buffer according to TTM mem
caching setting
Hi guys,
adding the usual suspects direct. Does anybody of hand know how to
check if an archit
Hi Thomas,
Am 03.03.21 um 09:49 schrieb Thomas Zimmermann:
Hi
Am 01.03.21 um 23:43 schrieb Oak Zeng:
If tbo.mem.bus.caching is cached, buffer is intended to be mapped
as cached from CPU. Map it with ioremap_cache.
Just a question for my understanding: This is on-device memory?
Accessing dev
Hi
Am 01.03.21 um 23:43 schrieb Oak Zeng:
If tbo.mem.bus.caching is cached, buffer is intended to be mapped
as cached from CPU. Map it with ioremap_cache.
Just a question for my understanding: This is on-device memory?
Accessing device memory is usually slow. If that memory can be mapped
wit
On Wed, 3 Mar 2021 at 08:45, Zeng, Oak wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
>
> Hi Daniel, Thomas, Dan,
>
>
>
> Does below message mean the calling ioremap_cache failed intel’s driver
> build? I can see both ioremap_cache and ioremap_wc are defined in
> arch/x86/mm/i
öm
(Intel)
Cc: Zeng, Oak ; kbuild-...@lists.01.org; Kuehling, Felix
; Kasiviswanathan, Harish
; Deucher, Alexander
; Huang, JinHuiEric ;
Koenig, Christian
Subject: Re: [PATCH] drm/ttm: ioremap buffer according to TTM mem caching
setting
Hi guys,
adding the usual suspects direct. Does anybo
Hi guys,
adding the usual suspects direct. Does anybody of hand know how to check
if an architecture supports ioremap_cache()?
For now we only need this on X86, but I would feel better if we don't
use an #ifdef here.
Regards,
Christian.
Am 02.03.21 um 05:12 schrieb kernel test robot:
Hi O
Hi Oak,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip linus/master v5.12-rc1 next-20210302]
[cannot apply to tegra-drm/drm/tegra/for-next drm-exynos/exynos-drm-next
drm/drm-next]
[If your patch is
Hi Oak,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip linus/master v5.12-rc1
next-20210301]
[cannot apply to tegra-drm/drm/tegra/for-next drm-exynos/exynos-drm-next
drm/drm-next]
[If your
If tbo.mem.bus.caching is cached, buffer is intended to be mapped
as cached from CPU. Map it with ioremap_cache.
This wasn't necessary before as device memory was never mapped
as cached from CPU side. It becomes necessary for aldebaran as
device memory is mapped cached from CPU.
Signed-off-by: Oa
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