[PATCH] drm/tegra: dpaux: Fix transfers larger than 4 bytes

2015-07-20 Thread Thierry Reding
On Mon, Jul 20, 2015 at 02:39:36AM -0500, Steev Klimaszewski wrote: > On Mon, Jul 20, 2015 at 1:49 AM, Thierry Reding > wrote: > > > From: Thierry Reding > > > > The DPAUX read/write FIFO registers aren't sequential in the register > > space, causing transfers larger than 4 bytes to cause access

[PATCH] drm/tegra: dpaux: Fix transfers larger than 4 bytes

2015-07-20 Thread Thierry Reding
From: Thierry Reding The DPAUX read/write FIFO registers aren't sequential in the register space, causing transfers larger than 4 bytes to cause accesses to non- existing FIFO registers. Fixes: 6b6b604215c6 ("drm/tegra: Add eDP support") Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/

[PATCH] drm/tegra: dpaux: Fix transfers larger than 4 bytes

2015-07-20 Thread Steev Klimaszewski
On Mon, Jul 20, 2015 at 1:49 AM, Thierry Reding wrote: > From: Thierry Reding > > The DPAUX read/write FIFO registers aren't sequential in the register > space, causing transfers larger than 4 bytes to cause accesses to non- > existing FIFO registers. > > Fixes: 6b6b604215c6 ("drm/tegra: Add eDP