The datasheet of V3s (and various other chips) wrote
that TCON0_DCLK_DIV can be >= 1 if only dclk is used,
and must >= 6 if dclk1 or dclk2 is used. As currently
neither dclk1 nor dclk2 is used (no writes to these
bits), let's set minimal division to 1.
If this minimal division is 6, some common do
Hi,
On Wed, Nov 13, 2019 at 01:27:25PM +, Tian Yunhao wrote:
> The datasheet of V3s (and various other chips) wrote
> that TCON0_DCLK_DIV can be >= 1 if only dclk is used,
> and must >= 6 if dclk1 or dclk2 is used. As currently
> neither dclk1 nor dclk2 is used (no writes to these
> bits), let
