On Wed, Jul 18, 2018 at 04:23:57PM +0200, Giulio Benetti wrote:
> Handle both positive and negative dclk polarity,
> according to bus_flags, taking care of this:
>
> On A20 and similar SoCs, the only way to achieve Positive Edge
> (Rising Edge), is setting dclk clock phase to 2/3(240°).
> By defau
Hi Paul,
can you give a try to this patch on A13 with VGA DAC?
Unfortunately I don't have an A13 board to test it.
Thanks in advance.
Giulio
Il 18/07/2018 16:23, Giulio Benetti ha scritto:
Handle both positive and negative dclk polarity,
according to bus_flags, taking care of this:
On A20 an
Handle both positive and negative dclk polarity,
according to bus_flags, taking care of this:
On A20 and similar SoCs, the only way to achieve Positive Edge
(Rising Edge), is setting dclk clock phase to 2/3(240°).
By default TCON works in Negative Edge(Falling Edge), this is why phase
is set to 0
