On 5/10/22 10:51, Raphael Gallais-Pou wrote:
On 5/5/22 19:40, Marek Vasut wrote:
On 5/4/22 09:59, Raphael Gallais-Pou wrote:
Hi Marek,
Hi,
[...]
@@ -499,8 +512,16 @@ static int dw_mipi_dsi_stm_probe(struct platform_device
*pdev)
}
dsi->hw_version = dsi_read(dsi, DSI_VERSIO
On 5/5/22 19:40, Marek Vasut wrote:
> On 5/4/22 09:59, Raphael Gallais-Pou wrote:
>> Hi Marek,
>
> Hi,
>
> [...]
>
>>> @@ -499,8 +512,16 @@ static int dw_mipi_dsi_stm_probe(struct platform_device
>>> *pdev)
>>> }
>>> dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
>>> +
>>>
On 5/4/22 09:59, Raphael Gallais-Pou wrote:
Hi Marek,
Hi,
[...]
@@ -499,8 +512,16 @@ static int dw_mipi_dsi_stm_probe(struct platform_device
*pdev)
}
dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
+
+ ret = dw_mipi_dsi_phy_regulator_on(dsi);
clk_disable
Hi Marek,
Thanks for your patch
On 4/29/22 22:45, Marek Vasut wrote:
> Certain DSI bridge chips like TC358767/TC358867/TC9595 expect the DSI D0
> data lane to be in LP-11 state when released from reset. Currently the
> STM32MP157 DSI host wrapper glue logic keeps D0 data lane in LP-00 state
> un
Certain DSI bridge chips like TC358767/TC358867/TC9595 expect the DSI D0
data lane to be in LP-11 state when released from reset. Currently the
STM32MP157 DSI host wrapper glue logic keeps D0 data lane in LP-00 state
until DSI init happens, which confuses the TC358767 into entering some
sort of tes
