On 5/26/23 11:05, Marek Vasut wrote:
On 5/15/23 18:02, Philippe CORNU wrote:
Hi,
The genmask of regsiter SSCR, BPCR & others were setted accordly to
the chipset stm32f4.
So that means:
F4 -> 2048x2048 framebuffer
H7/MP1 -> 4096x4096 framebuffer
?
Worse
F4 is 2048x2048
F7 is 4096x2048
M
On 5/15/23 18:02, Philippe CORNU wrote:
Hi,
The genmask of regsiter SSCR, BPCR & others were setted accordly to
the chipset stm32f4.
So that means:
F4 -> 2048x2048 framebuffer
H7/MP1 -> 4096x4096 framebuffer
?
Worse
F4 is 2048x2048
F7 is 4096x2048
MP1 is 4096x4096
and there is no IDR regi
On 10/14/22 19:15, Marek Vasut wrote:
On 10/14/22 17:55, Marek Vasut wrote:
On 10/14/22 15:42, Yannick FERTRE wrote:
Hi Marek,
Hello Yannick,
The genmask of regsiter SSCR, BPCR & others were setted accordly to
the chipset stm32f4.
So that means:
F4 -> 2048x2048 framebuffer
H7/MP1 -> 409
On 10/14/22 17:55, Marek Vasut wrote:
On 10/14/22 15:42, Yannick FERTRE wrote:
Hi Marek,
Hello Yannick,
The genmask of regsiter SSCR, BPCR & others were setted accordly to
the chipset stm32f4.
So that means:
F4 -> 2048x2048 framebuffer
H7/MP1 -> 4096x4096 framebuffer
?
Worse
F4 is 2048x
On 10/14/22 15:42, Yannick FERTRE wrote:
Hi Marek,
Hello Yannick,
The genmask of regsiter SSCR, BPCR & others were setted accordly to the
chipset stm32f4.
So that means:
F4 -> 2048x2048 framebuffer
H7/MP1 -> 4096x4096 framebuffer
?
We should then also update STM_MAX_FB_WIDTH/STM_MAX_FB_HEI
Hi Marek,
The genmask of regsiter SSCR, BPCR & others were setted accordly to the
chipset stm32f4.
You can see more details on page 493 of reference manual RM0090:
https://www.st.com/resource/en/reference_manual/DM00031020-.pdf
With future hardware, all of these registers will aligned on 16b
Hi Marek,
thanks for the patch.
Reviewed-by: Yannick Fertre
On 10/12/22 01:10, Marek Vasut wrote:
STM32MP15xx RM0436 Rev 6 "35.7.3 LTDC synchronization size configuration
register (LTDC_SSCR)" on page 1784 and onward indicates VSH and similar
bits are all [11:0] instead of [10:0] wide. Fix th
STM32MP15xx RM0436 Rev 6 "35.7.3 LTDC synchronization size configuration
register (LTDC_SSCR)" on page 1784 and onward indicates VSH and similar
bits are all [11:0] instead of [10:0] wide. Fix this.
[1] https://www.st.com/resource/en/reference_manual/DM00327659-.pdf
Fixes: b759012c5fa7 ("drm/stm:
