On Wednesday 6 July 2011, Jerome Glisse wrote:
> On Wed, Jul 6, 2011 at 12:29 PM, Simon Farnsworth
>
> > In particular, I'm a bit hazy about what the fence in pageflip is
> > doing - I assume it's there to synchronize drawing and scanout, so
> > that I don't flip to a buffer that's still being dr
The radeon pageflip ioctl handler delayed submitting the pageflip to
hardware until the vblank IRQ handler. On AMD Fusion (PALM GPU, G-T56N
CPU), when using a reduced blanking CVT mode, a pageflip submitted to
hardware in the IRQ handler failed to complete before the end of the
vblank, resulting in
On Wed, Jul 6, 2011 at 12:29 PM, Simon Farnsworth
wrote:
> The radeon pageflip ioctl handler delayed submitting the pageflip to
> hardware until the vblank IRQ handler. On AMD Fusion (PALM GPU, G-T56N
> CPU), when using a reduced blanking CVT mode, a pageflip submitted to
> hardware in the IRQ han
On Wednesday 6 July 2011, Jerome Glisse wrote:
> On Wed, Jul 6, 2011 at 12:29 PM, Simon Farnsworth
>
> > In particular, I'm a bit hazy about what the fence in pageflip is
> > doing - I assume it's there to synchronize drawing and scanout, so
> > that I don't flip to a buffer that's still being dr
On Wed, Jul 6, 2011 at 12:29 PM, Simon Farnsworth
wrote:
> The radeon pageflip ioctl handler delayed submitting the pageflip to
> hardware until the vblank IRQ handler. On AMD Fusion (PALM GPU, G-T56N
> CPU), when using a reduced blanking CVT mode, a pageflip submitted to
> hardware in the IRQ han
The radeon pageflip ioctl handler delayed submitting the pageflip to
hardware until the vblank IRQ handler. On AMD Fusion (PALM GPU, G-T56N
CPU), when using a reduced blanking CVT mode, a pageflip submitted to
hardware in the IRQ handler failed to complete before the end of the
vblank, resulting in
