Re: [PATCH] drm/msm/dpu: fix x1e80100 intf_6 underrun/vsync interrupt

On 11/15/2024 4:55 AM, Stephan Gerhold wrote: The IRQ indexes for the intf_6 underrun/vsync interrupts are swapped. DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16) is the actual underrun interrupt and DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17) is the vsync interrupt. This causes timeout errors when using the DP

Re: [PATCH] drm/msm/dpu: fix x1e80100 intf_6 underrun/vsync interrupt

On Fri, Nov 15, 2024 at 01:55:13PM +0100, Stephan Gerhold wrote: > The IRQ indexes for the intf_6 underrun/vsync interrupts are swapped. > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16) is the actual underrun interrupt and > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17) is the vsync interrupt. > > This causes timeout

Re: [PATCH] drm/msm/dpu: fix x1e80100 intf_6 underrun/vsync interrupt

On Fri, Nov 15, 2024 at 01:55:13PM +0100, Stephan Gerhold wrote: > The IRQ indexes for the intf_6 underrun/vsync interrupts are swapped. > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16) is the actual underrun interrupt and > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17) is the vsync interrupt. > > This causes timeout

[PATCH] drm/msm/dpu: fix x1e80100 intf_6 underrun/vsync interrupt

The IRQ indexes for the intf_6 underrun/vsync interrupts are swapped. DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16) is the actual underrun interrupt and DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17) is the vsync interrupt. This causes timeout errors when using the DP2 controller, e.g. [dpu error]enc37 frame done ti