On Fri, Jan 31, 2020 at 12:00 AM Akhil P Oommen wrote:
>
> On 1/24/2020 11:56 PM, Jordan Crouse wrote:
> > On Fri, Jan 24, 2020 at 05:50:11PM +0530, Akhil P Oommen wrote:
> >> Highest bank bit configuration is different for a618 gpu. Update
> >> it with the correct configuration which is the reset
On 1/24/2020 11:56 PM, Jordan Crouse wrote:
On Fri, Jan 24, 2020 at 05:50:11PM +0530, Akhil P Oommen wrote:
Highest bank bit configuration is different for a618 gpu. Update
it with the correct configuration which is the reset value incidentally.
Signed-off-by: Akhil P Oommen
Signed-off-by: Sha
Highest bank bit configuration is different for a618 gpu. Update
it with the correct configuration which is the reset value incidentally.
Signed-off-by: Akhil P Oommen
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++
1 file changed, 6 insertions(+), 4 del
On Fri, Jan 24, 2020 at 05:50:11PM +0530, Akhil P Oommen wrote:
> Highest bank bit configuration is different for a618 gpu. Update
> it with the correct configuration which is the reset value incidentally.
>
> Signed-off-by: Akhil P Oommen
> Signed-off-by: Sharat Masetty
> ---
> drivers/gpu/drm
On Fri, Jan 24, 2020 at 5:50 AM Akhil P Oommen wrote:
>
> Highest bank bit configuration is different for a618 gpu. Update
> it with the correct configuration which is the reset value incidentally.
>
> Signed-off-by: Akhil P Oommen
> Signed-off-by: Sharat Masetty
Thanks, this fixes the UBWC iss
