On Mon, May 17, 2021 at 03:30:45PM +0100, Paul Cercueil wrote:
> Hi Daniel,
>
> Le lun., mai 17 2021 at 15:15:59 +0200, Daniel Vetter a
> écrit :
> > On Thu, May 13, 2021 at 01:29:30PM +0100, Paul Cercueil wrote:
> > > Hi,
> > >
> > > Almost two months later,
> >
> > Since you're committer it
Hi Daniel,
Le lun., mai 17 2021 at 15:15:59 +0200, Daniel Vetter
a écrit :
On Thu, May 13, 2021 at 01:29:30PM +0100, Paul Cercueil wrote:
Hi,
Almost two months later,
Since you're committer it's expected that you go actively out to look
for
review or trade with someone else who has some
On Thu, May 13, 2021 at 01:29:30PM +0100, Paul Cercueil wrote:
> Hi,
>
> Almost two months later,
Since you're committer it's expected that you go actively out to look for
review or trade with someone else who has some patches that need a quick
look. It will not happen automatically, this is on y
Am 13.05.21 um 14:29 schrieb Paul Cercueil:
Hi,
Almost two months later,
Le mar., mars 23 2021 at 14:40:08 +, Paul Cercueil
a écrit :
When using a 24-bit panel on a 8-bit serial bus, the pixel clock
requested by the panel has to be multiplied by 3, since the subpixels
are shifted sequ
Hi,
Almost two months later,
Le mar., mars 23 2021 at 14:40:08 +, Paul Cercueil
a écrit :
When using a 24-bit panel on a 8-bit serial bus, the pixel clock
requested by the panel has to be multiplied by 3, since the subpixels
are shifted sequentially.
The code (in ingenic_drm_encoder_ato
> Am 12.04.2021 um 16:34 schrieb Paul Cercueil :
>
> Hi,
>
> Can I have an ACK for this patch?
>
> Then I can apply it to drm-misc-next-fixes.
>
> Cheers,
> -Paul
>
>
> Le mar. 23 mars 2021 à 14:40, Paul Cercueil a écrit :
>> When using a 24-bit panel on a 8-bit serial bus, the pixel clock
Hi,
Can I have an ACK for this patch?
Then I can apply it to drm-misc-next-fixes.
Cheers,
-Paul
Le mar. 23 mars 2021 à 14:40, Paul Cercueil a
écrit :
When using a 24-bit panel on a 8-bit serial bus, the pixel clock
requested by the panel has to be multiplied by 3, since the subpixels
are s
When using a 24-bit panel on a 8-bit serial bus, the pixel clock
requested by the panel has to be multiplied by 3, since the subpixels
are shifted sequentially.
The code (in ingenic_drm_encoder_atomic_check) already computed
crtc_state->adjusted_mode->crtc_clock accordingly, but clk_set_rate()
use
