[Now without the confidential header which shouldn't have spilled to
public lists, please reply to this one here.]
On Mon, Aug 05, 2013 at 01:24:15PM -0700, Furquan Shaikh wrote:
> We tested the submitted patch on several systems here and it seems to be
> working fine. So, I'm not sure I understan
On 05/08/2013 22:24, Furquan Shaikh wrote:
> We tested the submitted patch on several systems here and it seems to
> be working fine. So, I'm not sure I understand your comment. Can you
> please provide more details?
You check for the bit DP_PLL_FREQ_160MHZ in the register DP_A when
calculating
On 05/08/2013 22:24, Furquan Shaikh wrote:
We tested the submitted patch on several systems here and it seems to
be working fine. So, I'm not sure I understand your comment. Can you
please provide more details?
You check for the bit DP_PLL_FREQ_160MHZ in the register DP_A when
calculating the
We tested the submitted patch on several systems here and it seems to be
working fine. So, I'm not sure I understand your comment. Can you please
provide more details?
Thanks,
Furquan
On Mon, Aug 5, 2013 at 12:24 AM, Daniel Vetter wrote:
> On Thu, Aug 01, 2013 at 02:12:22PM -0700, Furquan Shai
On Thu, 1 Aug 2013 14:12:22 -0700
Furquan Shaikh wrote:
> @@ -1282,6 +1283,13 @@ static void intel_ddi_get_config(struct intel_encoder
> *encoder,
> flags |= DRM_MODE_FLAG_NVSYNC;
>
> pipe_config->adjusted_mode.flags |= flags;
> +
> + if (port == PORT_A) {
> +
On Thu, 1 Aug 2013 14:12:22 -0700
Furquan Shaikh wrote:
> @@ -1282,6 +1283,13 @@ static void intel_ddi_get_config(struct intel_encoder
> *encoder,
> flags |= DRM_MODE_FLAG_NVSYNC;
>
> pipe_config->adjusted_mode.flags |= flags;
> +
> + if (port == PORT_A) {
> +
[Now without the confidential header which shouldn't have spilled to
public lists, please reply to this one here.]
On Mon, Aug 05, 2013 at 01:24:15PM -0700, Furquan Shaikh wrote:
> We tested the submitted patch on several systems here and it seems to be
> working fine. So, I'm not sure I understan
We tested the submitted patch on several systems here and it seems to be
working fine. So, I'm not sure I understand your comment. Can you please
provide more details?
Thanks,
Furquan
On Mon, Aug 5, 2013 at 12:24 AM, Daniel Vetter wrote:
> On Thu, Aug 01, 2013 at 02:12:22PM -0700, Furquan Shai
On Thu, Aug 01, 2013 at 02:12:22PM -0700, Furquan Shaikh wrote:
> Enables getting correct mode clock when reading pipe config
>
> Signed-off-by: Furquan Shaikh
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 8
> drivers/gpu/drm/i915/intel_display.c | 9 -
> 2 files changed, 16 i
On Thu, Aug 01, 2013 at 02:12:22PM -0700, Furquan Shaikh wrote:
> Enables getting correct mode clock when reading pipe config
>
> Signed-off-by: Furquan Shaikh
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 8
> drivers/gpu/drm/i915/intel_display.c | 9 -
> 2 files changed, 16 i
Enables getting correct mode clock when reading pipe config
Signed-off-by: Furquan Shaikh
---
drivers/gpu/drm/i915/intel_ddi.c | 8
drivers/gpu/drm/i915/intel_display.c | 9 -
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/d
Enables getting correct mode clock when reading pipe config
Signed-off-by: Furquan Shaikh
---
drivers/gpu/drm/i915/intel_ddi.c | 8
drivers/gpu/drm/i915/intel_display.c | 9 -
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/d
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