[PATCH] drm/i915: Set i9xx sdvo clock limits according to specifications

2013-02-15 Thread Dave Airlie
On Fri, Feb 15, 2013 at 6:59 AM, Daniel Vetter wrote: > On Thu, Feb 14, 2013 at 08:50:25PM +, Chris Wilson wrote: >> On Wed, Feb 13, 2013 at 10:20:22PM +0100, Patrik Jakobsson wrote: >> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 >> > and 5-9. >> > Since we do al

[PATCH] drm/i915: Set i9xx sdvo clock limits according to specifications

2013-02-14 Thread Daniel Vetter
On Thu, Feb 14, 2013 at 10:45 PM, Dave Airlie wrote: > On Fri, Feb 15, 2013 at 6:59 AM, Daniel Vetter wrote: >> On Thu, Feb 14, 2013 at 08:50:25PM +, Chris Wilson wrote: >>> On Wed, Feb 13, 2013 at 10:20:22PM +0100, Patrik Jakobsson wrote: >>> > The Intel PRM says the M1 and M2 divisors must

[PATCH] drm/i915: Set i9xx sdvo clock limits according to specifications

2013-02-14 Thread Daniel Vetter
On Thu, Feb 14, 2013 at 08:50:25PM +, Chris Wilson wrote: > On Wed, Feb 13, 2013 at 10:20:22PM +0100, Patrik Jakobsson wrote: > > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and > > 5-9. > > Since we do all calculations based on them being register values (which are

[PATCH] drm/i915: Set i9xx sdvo clock limits according to specifications

2013-02-14 Thread Chris Wilson
On Wed, Feb 13, 2013 at 10:20:22PM +0100, Patrik Jakobsson wrote: > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and > 5-9. > Since we do all calculations based on them being register values (which are > subtracted by 2) we need to specify them accordingly. > > Signed-o

Re: [PATCH] drm/i915: Set i9xx sdvo clock limits according to specifications

2013-02-14 Thread Daniel Vetter
On Thu, Feb 14, 2013 at 10:45 PM, Dave Airlie wrote: > On Fri, Feb 15, 2013 at 6:59 AM, Daniel Vetter wrote: >> On Thu, Feb 14, 2013 at 08:50:25PM +, Chris Wilson wrote: >>> On Wed, Feb 13, 2013 at 10:20:22PM +0100, Patrik Jakobsson wrote: >>> > The Intel PRM says the M1 and M2 divisors must

Re: [PATCH] drm/i915: Set i9xx sdvo clock limits according to specifications

2013-02-14 Thread Dave Airlie
On Fri, Feb 15, 2013 at 6:59 AM, Daniel Vetter wrote: > On Thu, Feb 14, 2013 at 08:50:25PM +, Chris Wilson wrote: >> On Wed, Feb 13, 2013 at 10:20:22PM +0100, Patrik Jakobsson wrote: >> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 >> > and 5-9. >> > Since we do al

Re: [PATCH] drm/i915: Set i9xx sdvo clock limits according to specifications

2013-02-14 Thread Daniel Vetter
On Thu, Feb 14, 2013 at 08:50:25PM +, Chris Wilson wrote: > On Wed, Feb 13, 2013 at 10:20:22PM +0100, Patrik Jakobsson wrote: > > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and > > 5-9. > > Since we do all calculations based on them being register values (which are

Re: [PATCH] drm/i915: Set i9xx sdvo clock limits according to specifications

2013-02-14 Thread Chris Wilson
On Wed, Feb 13, 2013 at 10:20:22PM +0100, Patrik Jakobsson wrote: > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and > 5-9. > Since we do all calculations based on them being register values (which are > subtracted by 2) we need to specify them accordingly. > > Signed-o

[PATCH] drm/i915: Set i9xx sdvo clock limits according to specifications

2013-02-13 Thread Patrik Jakobsson
The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9. Since we do all calculations based on them being register values (which are subtracted by 2) we need to specify them accordingly. Signed-off-by: Patrik Jakobsson --- drivers/gpu/drm/i915/intel_display.c |4 ++--

[PATCH] drm/i915: Set i9xx sdvo clock limits according to specifications

2013-02-13 Thread Patrik Jakobsson
The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9. Since we do all calculations based on them being register values (which are subtracted by 2) we need to specify them accordingly. Signed-off-by: Patrik Jakobsson --- drivers/gpu/drm/i915/intel_display.c |4 ++--