Am Donnerstag, dem 12.06.2025 um 15:31 -0700 schrieb Doug Anderson:
> Hi,
>
> On Thu, Jun 12, 2025 at 10:52 AM Doug Anderson wrote:
> >
> > Hi,
> >
> > On Thu, Jun 12, 2025 at 12:35 AM Jayesh Choudhary
> > wrote:
> > >
> > > > > If refclk is described in devicetree node, then I see that
> >
Hi,
On Thu, Jun 12, 2025 at 10:52 AM Doug Anderson wrote:
>
> Hi,
>
> On Thu, Jun 12, 2025 at 12:35 AM Jayesh Choudhary wrote:
> >
> > >> If refclk is described in devicetree node, then I see that
> > >> the driver modifies it in every resume call based solely on the
> > >> clock value in dts.
>
Hi,
On Thu, Jun 12, 2025 at 12:35 AM Jayesh Choudhary wrote:
>
> >> If refclk is described in devicetree node, then I see that
> >> the driver modifies it in every resume call based solely on the
> >> clock value in dts.
> >
> > Exactly. But that is racy with what the chip itself is doing. I.e.
>
Hi Jayesh,
> + /*
> + * After EN is deasserted and an external clock is detected,
> the bridge
> + * will sample GPIO3:1 to determine its frequency. The
> driver will
> + * overwrite this setting. But this is racy. Thus we have to
>
Hello Michael,
On 10/06/25 12:45, Michael Walle wrote:
Hi Jayesh,
+ /*
+ * After EN is deasserted and an external clock is detected,
the bridge
+ * will sample GPIO3:1 to determine its frequency. The
driver will
+ * overwrite this setting. But this is racy. Thus we
Hi Jayesh,
+ /*
+* After EN is deasserted and an external clock is detected,
the bridge
+* will sample GPIO3:1 to determine its frequency. The driver
will
+* overwrite this setting. But this is racy. Thus we have to
wait a
+* couple of us. According to th
Hello Michael, Doug,
On 10/06/25 03:59, Doug Anderson wrote:
Hi,
On Wed, May 28, 2025 at 6:21 AM Michael Walle wrote:
The bridge has three bootstrap pins which are sampled to determine the
frequency of the external reference clock. The driver will also
(over)write that setting. But it seems
Hi,
On Wed, May 28, 2025 at 6:21 AM Michael Walle wrote:
>
> The bridge has three bootstrap pins which are sampled to determine the
> frequency of the external reference clock. The driver will also
> (over)write that setting. But it seems this is racy after the bridge is
> enabled. It was observe
The bridge has three bootstrap pins which are sampled to determine the
frequency of the external reference clock. The driver will also
(over)write that setting. But it seems this is racy after the bridge is
enabled. It was observed that although the driver write the correct
value (by sniffing on th
