Re: [PATCH] drm/bridge: ti-sn65dsi86: Fix output polarity setting bug

2022-11-30 Thread Doug Anderson
Hi, On Tue, Nov 29, 2022 at 9:46 PM Qiqi Zhang wrote: > > Hi, > > on Nov. 29, 2022, 11:45 a.m. Tomi wrote: > >On 29/11/2022 03:13, Doug Anderson wrote: > >> Hi, > >> > >> On Fri, Nov 25, 2022 at 2:54 AM Qiqi Zhang > >> wrote: > >>> > >>> According to the description in ti-sn65dsi86's datasheet:

Re: [PATCH] drm/bridge: ti-sn65dsi86: Fix output polarity setting bug

2022-11-30 Thread Qiqi Zhang
Hi, on Nov. 29, 2022, 11:45 a.m. Tomi wrote: >On 29/11/2022 03:13, Doug Anderson wrote: >> Hi, >> >> On Fri, Nov 25, 2022 at 2:54 AM Qiqi Zhang wrote: >>> >>> According to the description in ti-sn65dsi86's datasheet: >>> >>> CHA_HSYNC_POLARITY: >>> 0 = Active High Pulse. Synchronization signal is

Re: [PATCH] drm/bridge: ti-sn65dsi86: Fix output polarity setting bug

2022-11-29 Thread Tomi Valkeinen
On 29/11/2022 03:13, Doug Anderson wrote: Hi, On Fri, Nov 25, 2022 at 2:54 AM Qiqi Zhang wrote: According to the description in ti-sn65dsi86's datasheet: CHA_HSYNC_POLARITY: 0 = Active High Pulse. Synchronization signal is high for the sync pulse width. (default) 1 = Active Low Pulse. Synchr

Re: [PATCH] drm/bridge: ti-sn65dsi86: Fix output polarity setting bug

2022-11-28 Thread Doug Anderson
Hi, On Fri, Nov 25, 2022 at 2:54 AM Qiqi Zhang wrote: > > According to the description in ti-sn65dsi86's datasheet: > > CHA_HSYNC_POLARITY: > 0 = Active High Pulse. Synchronization signal is high for the sync > pulse width. (default) > 1 = Active Low Pulse. Synchronization signal is low for the s

Re: [PATCH] drm/bridge: ti-sn65dsi86: Fix output polarity setting bug

2022-11-27 Thread Laurent Pinchart
Adding Tomi to the CC list. Tomi, would you be able to test this ? On Fri, Nov 25, 2022 at 06:45:58PM +0800, Qiqi Zhang wrote: > According to the description in ti-sn65dsi86's datasheet: > > CHA_HSYNC_POLARITY: > 0 = Active High Pulse. Synchronization signal is high for the sync > pulse width. (d

[PATCH] drm/bridge: ti-sn65dsi86: Fix output polarity setting bug

2022-11-26 Thread Qiqi Zhang
According to the description in ti-sn65dsi86's datasheet: CHA_HSYNC_POLARITY: 0 = Active High Pulse. Synchronization signal is high for the sync pulse width. (default) 1 = Active Low Pulse. Synchronization signal is low for the sync pulse width. CHA_VSYNC_POLARITY: 0 = Active High Pulse. Synchron